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mb/google/mancomb: Add STAPM values to overridetree 

Follow the FP6 IRM(#56328) to set the stapm parameter
and allow other mancomb variants boards can customize those parameters.

BUG=b:1181157669
TEST=build.

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ib3ed76e5212a5a8b5fb4fcc3d6884ceff82377b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Chris Wang 2021-04-28 00:03:03 +08:00 committed by Felix Held
parent 66e35fb341
commit ca084b8db2
2 changed files with 10 additions and 0 deletions
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2
src/mainboard/google/mancomb/variants/baseboard/devicetree.cb
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@ -1,6 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-or-later # SPDX-License-Identifier: GPL-2.0-or-later
chip soc/amd/cezanne chip soc/amd/cezanne
register "system_configuration" = "3"
# eSPI Configuration # eSPI Configuration
register "common_config.espi_config" = "{ register "common_config.espi_config" = "{
.std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN, .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN,

8
src/mainboard/google/mancomb/variants/mancomb/overridetree.cb
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@ -1,4 +1,12 @@
chip soc/amd/cezanne chip soc/amd/cezanne
register "slow_ppt_limit_mW" = "37500"
register "fast_ppt_limit_mW" = "48000"
register "slow_ppt_time_constant_s" = "5"
register "stapm_time_constant_s" = "275"
register "sustained_power_limit_mW" = "25000"
register "thermctl_limit_degreeC" = "100"
device domain 0 on device domain 0 on
end # domain end # domain