mb/google/{glados,dragonegg}: Configure GPIOs in mainboard chip->init()

mainboard_silicon_init_params() is supposed to be used for only
overriding any FSP params as per mainboard configuration. GPIOs should
be configured by mainboard as part of its chip init(). This ensures
proper ordering w.r.t. any common operations that the SoC code might
want to perform e.g. snapshot ITSS polarities.

This change moves the configuration of GPIOs from
mainboard_silicon_init_params() to mainboard chip->init().

Change-Id: I5d10c01c5b9d5f8ed02274d51dcf9c2a17269685
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36270
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/dragonegg/Makefile.inc

@@ -24,7 +24,6 @@ romstage-y += romstage_fsp_params.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
 ramstage-y += mainboard.c
-ramstage-y += ramstage.c
 
 smm-y += smihandler.c
 

src/mainboard/google/dragonegg/mainboard.c

@@ -23,6 +23,12 @@
 
 static void mainboard_init(void *chip_info)
 {
+	size_t num;
+	const struct pad_config *gpio_table;
+
+	gpio_table = variant_gpio_table(&num);
+	gpio_configure_pads(gpio_table, num);
+
 	mainboard_ec_init();
 }
 

src/mainboard/google/dragonegg/ramstage.c

@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2018 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <baseboard/variants.h>
-#include <soc/ramstage.h>
-#include <variant/gpio.h>
-
-void mainboard_silicon_init_params(FSP_S_CONFIG *params)
-{
-	size_t num;
-	const struct pad_config *gpio_table;
-
-	gpio_table = variant_gpio_table(&num);
-	gpio_configure_pads(gpio_table, num);
-}

src/mainboard/google/glados/Makefile.inc

@@ -27,7 +27,6 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
 
 ramstage-y += mainboard.c
-ramstage-y += ramstage.c
 
 smm-y += smihandler.c
 

src/mainboard/google/glados/mainboard.c

@@ -115,6 +115,14 @@ static void mainboard_enable(struct device *dev)
 	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 }
 
+static void mainboard_chip_init(void *chip_info)
+{
+	/* Configure pads prior to SiliconInit() in case there's any
+	 * dependencies during hardware initialization. */
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
+
 struct chip_operations mainboard_ops = {
+	.init = mainboard_chip_init,
 	.enable_dev = mainboard_enable,
 };

src/mainboard/google/glados/ramstage.c

@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Intel Corporation
- * Copyright (C) 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <soc/ramstage.h>
-#include <variant/gpio.h>
-
-void mainboard_silicon_init_params(FSP_SIL_UPD *params)
-{
-	/* Configure pads prior to SiliconInit() in case there's any
-	 * dependencies during hardware initialization. */
-	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
-}