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mb/intel/tglrvp: Enable Intel Speed Shift Technology for Tigerlake RVP

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BUG=none
TEST=Build for Tigerlake RVP and boot to OS. Test if following sysfs is populated.
cat /sys/devices/system/cpu/intel_pstate/

Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Change-Id: Ie3d9691e149a6fbc19c6691896126d04c680fde3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45609
Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Shreesh Chhabbi 2020-08-27 16:41:42 -07:00 committed by Tim Wawrzynczak
parent 5b7daa224c
commit ca128a0eb4
2 changed files with 6 additions and 0 deletions
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3
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
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@ -115,6 +115,9 @@ chip soc/intel/tigerlake
register "TcssXhciEn" = "1"
register "TcssAuxOri" = "0"
# Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"
# Enable S0ix
register "s0ix_enable" = "1"

3
src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
View file

@ -109,6 +109,9 @@ chip soc/intel/tigerlake
register "TcssXhciEn" = "1"
register "TcssAuxOri" = "0"
# Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"
# Enable S0ix
register "s0ix_enable" = "1"