diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index 3e72da3aa9..5a0a442161 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -566,21 +566,83 @@ Use the following steps to debug the call to TempRamInit:

FADT

The EDK2 module - CorebootModulePkg/CbSupportPei/CbSupportPei.c - requires that the FADT contains the following values: + CorebootModulePkg/Library/CbParseLib/CbParseLib.c + requires that the FADT contains the values in the table below. + These values are placed into a HOB identified by + gUefiAcpiBoardInfoGuid + by routine + CorebootModulePkg/CbSupportPei/CbSupportPei/CbPeiEntryPoint.

- + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - -
EDK2 Field Coreboot FieldEDK2 FieldgUefiAcpiBoardInfoGuidUse + + ACPI Spec. + Section +
gpe0_blk
gpe0_blk_len		Gpe0Blk
Gpe0BlkLen		 + PmGpeEnBase + Shutdown4.8.4.1
pm1a_cnt_blkPm1aCntBlkPmCtrlRegBase + Shutdown
+ Suspend + 		4.8.3.2.1
pm1a_evt_blkPm1aEvtBlkPmEvtBaseShutdown4.8.3.1.1
pm_tmr_blkPmTmrBlkPmTimerRegBase + Timer + 4.8.3.3
reset_reg.ResetReg.AddressResetRegAddress + Cold + and + Warm + resets + 4.3.3.6
reset_valueResetValueResetValue + Cold + and + Warm + resets + 4.8.3.6
Pm1aCntBlkpm1a_cnt_blk
PmTmrBlkpm_tmr_blk
ResetReg.Addressreset_reg.
ResetValuereset_value
Pm1aEvtBlkpm1a_evt_blk
Gpe0Blkgpe0_blk
Gpe0BlkLengpe0_blk_len

The EDK2 data structure is defined in @@ -603,6 +665,6 @@ Use the following steps to debug the call to TempRamInit:

-

Modified: 20 February 2016

+

Modified: 28 February 2016

\ No newline at end of file diff --git a/Documentation/Intel/index.html b/Documentation/Intel/index.html index 5a622a9dd9..61d14c861f 100644 --- a/Documentation/Intel/index.html +++ b/Documentation/Intel/index.html @@ -30,6 +30,7 @@

Documentation