nb/intel/sandybridge: Correct TC_DTP handling
It is only for Ivy Bridge, and needs to be set on certain circumstances. Change-Id: I4093adef44fae787c96fec4b4b8c7c867786d219 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -216,8 +216,22 @@ void dram_timing_regs(ramctr_timing *ctrl)
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printram("OTHP [%x] = %x\n", addr, reg);
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MCHBAR32(addr) = reg;
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/* FIXME: This register only exists on Ivy Bridge! */
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MCHBAR32(TC_DTP_ch(channel)) = 0;
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/* Debug parameters - only applies to Ivy Bridge */
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if (IS_IVY_CPU(ctrl->cpu)) {
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reg = 0;
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/*
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* If tXP and tXPDLL are very high, we need to increase them by one.
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* This can only happen on Ivy Bridge, and when overclocking the RAM.
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*/
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if (ctrl->tXP >= 8)
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reg |= (1 << 12);
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if (ctrl->tXPDLL >= 32)
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reg |= (1 << 13);
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MCHBAR32(TC_DTP_ch(channel)) = reg;
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}
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MCHBAR32_OR(addr, 0x00020000);
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