diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index 739a849715..d3aab62a68 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -163,6 +163,9 @@ chip soc/intel/cannonlake
 
 	register "tcc_offset" = "10"
 
+	# PCH Thermal Trip Temperature in deg C
+	register "common_soc_config.pch_thermal_trip" = "77"
+
 	register "common_soc_config" = "{
 		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
 		.i2c[0] = {