nb/intel/gm45: Remove UMA alignment optimization
This code path was only triggered in one corner case: GFX UMA set to 48MiB. It created a hole below UMA to save MTRRs. But, this hole was never accounted for when calculating cbmem_top(). Instead of trying to fix it, remove it, it's not worth the trouble. TEST=Booted lenovo/x200 with all available CMOS gfx_uma_size settings. Change-Id: I3f4ceec4224d86113be9bfa3ce4759bed584640d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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@ -71,7 +71,7 @@ static int decode_pcie_bar(u32 *const base, u32 *const len)
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static void mch_domain_read_resources(device_t dev)
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{
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u64 tom, touud;
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u32 tomk, tolud, uma_sizek = 0, usable_tomk;
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u32 tomk, tolud, uma_sizek = 0;
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u32 pcie_config_base, pcie_config_size;
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/* Total Memory 2GB example:
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@ -130,16 +130,12 @@ static void mch_domain_read_resources(device_t dev)
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uma_sizek = gms_sizek + gsm_sizek;
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}
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usable_tomk = ALIGN_DOWN(tomk, 64 << 10);
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if (tomk - usable_tomk > (16 << 10))
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usable_tomk = tomk;
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printk(BIOS_INFO, "Available memory below 4GB: %uM\n", usable_tomk >> 10);
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printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10);
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/* Report the memory regions */
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ram_resource(dev, 3, 0, legacy_hole_base_k);
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ram_resource(dev, 4, legacy_hole_base_k + legacy_hole_size_k,
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(usable_tomk - (legacy_hole_base_k + legacy_hole_size_k)));
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(tomk - (legacy_hole_base_k + legacy_hole_size_k)));
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/*
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* If >= 4GB installed then memory from TOLUD to 4GB
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@ -1241,10 +1241,6 @@ static void program_memory_map(const dimminfo_t *const dimms, const channel_mode
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printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10);
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uma_sizem = (gms_sizek + gsm_sizek) >> 10;
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/* Further reduce MTRR usage if it costs use less than
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16 MiB. */
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if (ALIGN_UP(uma_sizem, 64) - uma_sizem <= 16)
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uma_sizem = ALIGN_UP(uma_sizem, 64);
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}
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}
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