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sb/intel/i82801jx: Fix 16-bit read/write PCI_COMMAND register 

Change-Id: If39cdfb21fec307141593f2482e014e146d4f1f2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS 2020-04-28 10:29:11 +02:00 committed by Patrick Georgi
parent b9d2e228b6
commit ca4ff25290
4 changed files with 4 additions and 15 deletions
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3
src/southbridge/intel/i82801jx/hdaudio.c
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@ -247,8 +247,7 @@ static void azalia_init(struct device *dev)
pci_write_config32(dev, 0x120, reg32); pci_write_config32(dev, 0x120, reg32);
/* Set Bus Master */ /* Set Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
reg8 = pci_read_config8(dev, 0x4d); // Docking Status reg8 = pci_read_config8(dev, 0x4d); // Docking Status
reg8 &= ~(1 << 7); // Docking not supported reg8 &= ~(1 << 7); // Docking not supported

6
src/southbridge/intel/i82801jx/i82801jx.c
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@ -13,12 +13,8 @@ typedef struct southbridge_intel_i82801jx_config config_t;
static void i82801jx_enable_device(struct device *dev) static void i82801jx_enable_device(struct device *dev)
{ {
u32 reg32;
/* Enable SERR */ /* Enable SERR */
reg32 = pci_read_config32(dev, PCI_COMMAND); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
reg32 |= PCI_COMMAND_SERR;
pci_write_config32(dev, PCI_COMMAND, reg32);
} }
static void i82801jx_early_settings(const config_t *const info) static void i82801jx_early_settings(const config_t *const info)

4
src/southbridge/intel/i82801jx/pcie.c
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@ -20,9 +20,7 @@ static void pci_init(struct device *dev)
printk(BIOS_DEBUG, "Initializing ICH10 PCIe root port.\n"); printk(BIOS_DEBUG, "Initializing ICH10 PCIe root port.\n");
/* Enable Bus Master */ /* Enable Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
reg32 |= PCI_COMMAND_MASTER;
pci_write_config32(dev, PCI_COMMAND, reg32);
/* Set Cache Line Size to 0x10 */ /* Set Cache Line Size to 0x10 */
// This has no effect but the OS might expect it // This has no effect but the OS might expect it

6
src/southbridge/intel/i82801jx/usb_ehci.c
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@ -11,12 +11,8 @@
static void usb_ehci_init(struct device *dev) static void usb_ehci_init(struct device *dev)
{ {
u32 reg32;
printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
reg32 = pci_read_config32(dev, PCI_COMMAND); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
reg32 |= PCI_COMMAND_MASTER;
pci_write_config32(dev, PCI_COMMAND, reg32);
printk(BIOS_DEBUG, "done.\n"); printk(BIOS_DEBUG, "done.\n");
} }