soc/intel/xeon_sp: use get_socket_ubox_busno() to hide soc specifics

Intel SPR-SP has its specific way to get the bus number of ubox.
Move the current implementations to CPX-SP and SKX-SP folders.

Change-Id: I2b69be74d140115f9f78bc991fb690e3c90c88db
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>

src/soc/intel/xeon_sp/cpx/Makefile.inc

@@ -5,7 +5,7 @@ ifeq ($(CONFIG_SOC_INTEL_COOPERLAKE_SP),y)
 subdirs-y += ../../../../cpu/intel/turbo
 subdirs-y += ../../../../cpu/intel/microcode
 
-romstage-y += romstage.c ddr.c
+romstage-y += romstage.c ddr.c soc_util.c
 romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
 romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
 

src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h

@@ -8,7 +8,9 @@
 
 const struct SystemMemoryMapHob *get_system_memory_map(void);
 
+uint8_t get_stack_busno(const uint8_t stack);
 uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack);
+uint32_t get_socket_ubox_busno(uint32_t socket);
 
 int soc_get_stack_for_port(int port);
 

src/soc/intel/xeon_sp/cpx/soc_util.c

@@ -29,6 +29,17 @@ bool is_iio_stack_res(const STACK_RES *res)
 	return res->Personality == TYPE_UBOX_IIO;
 }
 
+uint8_t get_stack_busno(const uint8_t stack)
+{
+	if (stack >= MAX_IIO_STACK) {
+		printk(BIOS_ERR, "%s: Stack %u does not exist!\n", __func__, stack);
+		return 0;
+	}
+	const pci_devfn_t dev = PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC);
+	const uint16_t offset = stack / 4 ? UBOX_DECS_CPUBUSNO1_CSR : UBOX_DECS_CPUBUSNO_CSR;
+	return pci_io_read_config32(dev, offset) >> (8 * (stack % 4)) & 0xff;
+}
+
 uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack)
 {
 	const IIO_UDS *hob = get_iio_uds();
@@ -38,6 +49,14 @@ uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack)
 	return hob->PlatformData.IIO_resource[socket].StackRes[stack].BusBase;
 }
 
+uint32_t get_socket_ubox_busno(uint32_t socket)
+{
+	if (socket == 0)
+		return get_stack_busno(PCU_IIO_STACK);
+
+	return get_socket_stack_busno(socket, PCU_IIO_STACK);
+}
+
 /*
  * EX: CPX-SP
  * Ports    Stack   Stack(HOB)  IioConfigIou

src/soc/intel/xeon_sp/include/soc/util.h

@@ -7,7 +7,6 @@
 #include <hob_iiouds.h>
 
 void unlock_pam_regions(void);
-uint8_t get_stack_busno(const uint8_t stack);
 msr_t read_msr_ppin(void);
 int get_platform_thread_count(void);
 const IIO_UDS *get_iio_uds(void);

src/soc/intel/xeon_sp/skx/include/soc/soc_util.h

@@ -10,7 +10,9 @@ void config_reset_cpl3_csrs(void);
 
 const struct SystemMemoryMapHob *get_system_memory_map(void);
 
+uint8_t get_stack_busno(const uint8_t stack);
 uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack);
+uint32_t get_socket_ubox_busno(uint32_t socket);
 
 int soc_get_stack_for_port(int port);
 

src/soc/intel/xeon_sp/skx/soc_util.c

@@ -60,6 +60,17 @@ bool is_iio_stack_res(const STACK_RES *res)
 	return res->BusBase < res->BusLimit;
 }
 
+uint8_t get_stack_busno(const uint8_t stack)
+{
+	if (stack >= MAX_IIO_STACK) {
+		printk(BIOS_ERR, "%s: Stack %u does not exist!\n", __func__, stack);
+		return 0;
+	}
+	const pci_devfn_t dev = PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC);
+	const uint16_t offset = stack / 4 ? UBOX_DECS_CPUBUSNO1_CSR : UBOX_DECS_CPUBUSNO_CSR;
+	return pci_io_read_config32(dev, offset) >> (8 * (stack % 4)) & 0xff;
+}
+
 uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack)
 {
 	const IIO_UDS *hob = get_iio_uds();
@@ -69,6 +80,14 @@ uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack)
 	return hob->PlatformData.CpuQpiInfo[socket].StackBus[stack];
 }
 
+uint32_t get_socket_ubox_busno(uint32_t socket)
+{
+	if (socket == 0)
+		return get_stack_busno(PCU_IIO_STACK);
+
+	return get_socket_stack_busno(socket, PCU_IIO_STACK);
+}
+
 void config_reset_cpl3_csrs(void)
 {
 	uint32_t data, plat_info, max_min_turbo_limit_ratio;

src/soc/intel/xeon_sp/util.c

@@ -13,22 +13,11 @@
 #include <soc/util.h>
 #include <timer.h>
 
-uint8_t get_stack_busno(const uint8_t stack)
-{
-	if (stack >= MAX_IIO_STACK) {
-		printk(BIOS_ERR, "%s: Stack %u does not exist!\n", __func__, stack);
-		return 0;
-	}
-	const pci_devfn_t dev = PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC);
-	const uint16_t offset = stack / 4 ? UBOX_DECS_CPUBUSNO1_CSR : UBOX_DECS_CPUBUSNO_CSR;
-	return pci_io_read_config32(dev, offset) >> (8 * (stack % 4)) & 0xff;
-}
-
 void unlock_pam_regions(void)
 {
 	uint32_t pam0123_unlock_dram = 0x33333330;
 	uint32_t pam456_unlock_dram = 0x00333333;
-	uint32_t bus1 = get_stack_busno(1);
+	uint32_t bus1 = get_socket_ubox_busno(0);
 
 	pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC),
 		SAD_ALL_PAM0123_CSR, pam0123_unlock_dram);
@@ -270,7 +259,7 @@ static bool write_bios_mailbox_cmd(pci_devfn_t dev, uint32_t command, uint32_t d
 static bool set_bios_reset_cpl_for_package(uint32_t socket, uint32_t rst_cpl_mask,
 	uint32_t pcode_init_mask, uint32_t val)
 {
-	const uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK);
+	const uint32_t bus = get_socket_ubox_busno(socket);
 	const pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN);
 
 	uint32_t reg = pci_s_read_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG);
@@ -289,7 +278,7 @@ static void set_bios_init_completion_for_package(uint32_t socket)
 {
 	uint32_t data;
 	bool timedout;
-	const uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK);
+	const uint32_t bus = get_socket_ubox_busno(socket);
 	const pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN);
 
 	/* read PCU config */