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AMD S3: Program the flash in a bigger data packet 

According to spi.c in src/southbridge/amd/agesa/hudson
readwrite = (bytesin + readoffby1) << 4 | bytesout;
We can see that Hudson limits the SPI programming data
packet size as 15.

We used to write data to SPI in dword mode. It didn't
take full advantage of the data packet size. We need to
leverage that to speed up programming time.

Change-Id: I615e3c8e754e58702247bc26cfffbedaf5827ea8
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/2306
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
This commit is contained in:
Zheng Bao 2013-02-17 17:27:46 +08:00 committed by Patrick Georgi
parent 178df1121d
commit ca6e1f6c04
1 changed files with 22 additions and 34 deletions
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56
src/cpu/amd/agesa/s3_resume.c
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@ -178,29 +178,21 @@ void OemAgesaSaveMtrr(void)
/* Fixed MTRRs */ /* Fixed MTRRs */
msr_data = rdmsr(0x250); msr_data = rdmsr(0x250);
flash->write(flash, nvram_pos, 4, &msr_data.lo); flash->write(flash, nvram_pos, 8, &msr_data);
nvram_pos += 4; nvram_pos += 8;
flash->write(flash, nvram_pos, 4, &msr_data.hi);
nvram_pos += 4;
msr_data = rdmsr(0x258); msr_data = rdmsr(0x258);
flash->write(flash, nvram_pos, 4, &msr_data.lo); flash->write(flash, nvram_pos, 8, &msr_data);
nvram_pos += 4; nvram_pos += 8;
flash->write(flash, nvram_pos, 4, &msr_data.hi);
nvram_pos += 4;
msr_data = rdmsr(0x259); msr_data = rdmsr(0x259);
flash->write(flash, nvram_pos, 4, &msr_data.lo); flash->write(flash, nvram_pos, 8, &msr_data);
nvram_pos += 4; nvram_pos += 8;
flash->write(flash, nvram_pos, 4, &msr_data.hi);
nvram_pos += 4;
for (i = 0x268; i < 0x270; i++) { for (i = 0x268; i < 0x270; i++) {
msr_data = rdmsr(i); msr_data = rdmsr(i);
flash->write(flash, nvram_pos, 4, &msr_data.lo); flash->write(flash, nvram_pos, 8, &msr_data);
nvram_pos += 4; nvram_pos += 8;
flash->write(flash, nvram_pos, 4, &msr_data.hi);
nvram_pos += 4;
} }
/* Disable access to AMD RdDram and WrDram extension bits */ /* Disable access to AMD RdDram and WrDram extension bits */
@ -211,32 +203,24 @@ void OemAgesaSaveMtrr(void)
/* Variable MTRRs */ /* Variable MTRRs */
for (i = 0x200; i < 0x210; i++) { for (i = 0x200; i < 0x210; i++) {
msr_data = rdmsr(i); msr_data = rdmsr(i);
flash->write(flash, nvram_pos, 4, &msr_data.lo); flash->write(flash, nvram_pos, 8, &msr_data);
nvram_pos += 4; nvram_pos += 8;
flash->write(flash, nvram_pos, 4, &msr_data.hi);
nvram_pos += 4;
} }
/* SYS_CFG */ /* SYS_CFG */
msr_data = rdmsr(0xC0010010); msr_data = rdmsr(0xC0010010);
flash->write(flash, nvram_pos, 4, &msr_data.lo); flash->write(flash, nvram_pos, 8, &msr_data);
nvram_pos += 4; nvram_pos += 8;
flash->write(flash, nvram_pos, 4, &msr_data.hi);
nvram_pos += 4;
/* TOM */ /* TOM */
msr_data = rdmsr(0xC001001A); msr_data = rdmsr(0xC001001A);
flash->write(flash, nvram_pos, 4, &msr_data.lo); flash->write(flash, nvram_pos, 8, &msr_data);
nvram_pos += 4; nvram_pos += 8;
flash->write(flash, nvram_pos, 4, &msr_data.hi);
nvram_pos += 4;
/* TOM2 */ /* TOM2 */
msr_data = rdmsr(0xC001001D); msr_data = rdmsr(0xC001001D);
flash->write(flash, nvram_pos, 4, &msr_data.lo); flash->write(flash, nvram_pos, 8, &msr_data);
nvram_pos += 4; nvram_pos += 8;
flash->write(flash, nvram_pos, 4, &msr_data.hi);
nvram_pos += 4;
flash->spi->rw = SPI_WRITE_FLAG; flash->spi->rw = SPI_WRITE_FLAG;
spi_release_bus(flash->spi); spi_release_bus(flash->spi);
@ -290,13 +274,17 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data)
flash->erase(flash, S3_DATA_VOLATILE_POS, S3_DATA_VOLATILE_SIZE); flash->erase(flash, S3_DATA_VOLATILE_POS, S3_DATA_VOLATILE_SIZE);
} }
#ifndef SPI_DATA_PACKET_SIZE
#define SPI_DATA_PACKET_SIZE 0xF
#endif
nvram_pos = 0; nvram_pos = 0;
flash->write(flash, nvram_pos + pos, sizeof(DataSize), &DataSize); flash->write(flash, nvram_pos + pos, sizeof(DataSize), &DataSize);
for (nvram_pos = 0; nvram_pos < DataSize; nvram_pos += 4) { for (nvram_pos = 0; nvram_pos < DataSize - SPI_DATA_PACKET_SIZE; nvram_pos += SPI_DATA_PACKET_SIZE) {
data = *(u32 *) (Data + nvram_pos); data = *(u32 *) (Data + nvram_pos);
flash->write(flash, nvram_pos + pos + 4, sizeof(u32), (u32 *)(Data + nvram_pos)); flash->write(flash, nvram_pos + pos + 4, SPI_DATA_PACKET_SIZE, (u8 *)(Data + nvram_pos));
} }
flash->write(flash, nvram_pos + pos + 4, DataSize % SPI_DATA_PACKET_SIZE, (u8 *)(Data + nvram_pos));
flash->spi->rw = SPI_WRITE_FLAG; flash->spi->rw = SPI_WRITE_FLAG;
spi_release_bus(flash->spi); spi_release_bus(flash->spi);