soc/intel/adl: Add missing claimed memory regions
The Alder Lake chipset has several more reserved memory regions that are unavailable to the resource allocator than are currently marked as such in the system agent code. This CL adds the following regions (documented in Intel docs #626540, #619503): 1. TSEG 2. GSM 3. DSM 4. PCH_RESERVED 5. CRAB_ABORT 6. APIC 7. TPM 8. LT_SECURITY Claimed regions before this change: ======================================================== base 0 size a0000 // 0 - > 0xa0000 base a0000 size 20000 // legacy VGA base c0000 size 40000 // RAM base c0000 size 76f40000 // 0xc0000 -> top_of_ram base 77000000 size 9400000 // top_of_ram -> TOLUD base c0000000 size 10000000 // PCIEXBAR base f8000000 size 2000000 // MMSPI base fb000000 size 1000 // REGBAR base fed80000 size 4000 // EDRAMBAR base fed84000 size 1000 // TBT0BAR base fed85000 size 1000 // TBT1BAR base fed86000 size 1000 // TBT2BAR base fed87000 size 1000 // TBT3BAR base fed90000 size 1000 // GFXVTBAR base fed91000 size 1000 // VTVC0BAR base fed92000 size 1000 // IPUVTBAR base feda0000 size 1000 // DMIBAR base feda1000 size 1000 // EPBAR base fedc0000 size 20000 // MCHBAR base 100000000 size 17fc00000 // 4GiB -> TOUUD Claimed regions with this change: ======================================================== base 0 size a0000 // 0 - > 0xa0000 base a0000 size 20000 // legacy VGA base c0000 size 40000 // RAM base c0000 size 76f40000 // 0xc0000 -> top_of_ram base 77000000 size 9400000 // top_of_ram -> TOLUD base 7b800000 size 800000 // TSEG base 7c000000 size 800000 // GSM base 7c800000 size 3c00000 // DSM base c0000000 size 10000000 // PCIEXBAR base f8000000 size 2000000 // MMSPI base fb000000 size 1000 // REGBAR base fc800000 size 2000000 // PCH_RESERVED base feb00000 size 80000 // CRAB_ABORT base fec00000 size 100000 // APIC base fed40000 size 10000 // TPM base fed50000 size 20000 // LT_SECURITY base fed80000 size 4000 // EDRAMBAR base fed84000 size 1000 // TBT0BAR base fed85000 size 1000 // TBT1BAR base fed86000 size 1000 // TBT2BAR base fed87000 size 1000 // TBT3BAR base fed90000 size 1000 // GFXVTBAR base fed91000 size 1000 // VTVC0BAR base fed92000 size 1000 // IPUVTBAR base feda0000 size 1000 // DMIBAR base feda1000 size 1000 // EPBAR base fedc0000 size 20000 // MCHBAR base 100000000 size 17fc00000 // 4GiB -> TOUUD BUG=b:149830546 BRANCH=firmware-brya-14505.B TEST='emerge-brya coreboot chromeos-bootimage' builds correctly. Tested on an Anahera device which successfully boots to ChromeOS with kernel version 5.10.109-15688-g857e654d1705. Also ran dmseg, and saw the added regions in e820 prints. Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I058a5c1cc59703e35ceddb8a7e26fb22a6a2b75e Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Eran Mitrani
Felix Held
parent
400c30005e
commit
ca741055e6
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@ -55,4 +55,30 @@ static const struct sa_mmio_descriptor soc_vtd_resources[] = {
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#define V_P2SB_CFG_HBDF_DEV 30
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#define V_P2SB_CFG_HBDF_FUNC 6
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#define CRAB_ABORT_BASE_ADDR 0xFEB00000
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#define CRAB_ABORT_SIZE (512 * KiB)
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#define TPM_BASE_ADDRESS 0xFED40000
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#define TPM_SIZE (64 * KiB)
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#define LT_SECURITY_BASE_ADDR 0xFED50000
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#define LT_SECURITY_SIZE (128 * KiB)
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#define APIC_SIZE (1 * MiB)
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#define MASK_PCIEXBAR_LENGTH 0x0000000E // bits [3:1]
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#define PCIEXBAR_LENGTH_LSB 1 // used to shift right
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#define DSM_BASE_ADDR_REG 0xB0
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#define MASK_DSM_LENGTH 0xFF00 // [15:8]
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#define MASK_DSM_LENGTH_LSB 8 // used to shift right
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#define MASK_GSM_LENGTH 0xC0 // [7:6]
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#define MASK_GSM_LENGTH_LSB 6 // used to shift right
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#define DPR_REG 0x5C
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#define MASK_DPR_LENGTH 0xFF0 // [11:4]
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#define MASK_DPR_LENGTH_LSB 4 // used to shift right
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uint64_t get_mmcfg_size(struct device *dev);
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uint64_t get_dsm_size(struct device *dev);
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uint64_t get_gsm_size(struct device *dev);
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uint64_t get_dpr_size(struct device *dev);
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#endif
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@ -6,15 +6,20 @@
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* Chapter number: 3
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*/
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#include <arch/ioapic.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <delay.h>
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#include <intelblocks/cpulib.h>
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#include <intelblocks/msr.h>
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#include <intelblocks/power_limit.h>
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#include <intelblocks/systemagent.h>
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#include <soc/iomap.h>
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#include <soc/soc_chip.h>
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#include <soc/systemagent.h>
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#include <spi_flash.h>
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#include "stddef.h"
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/*
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* SoC implementation
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@ -25,13 +30,22 @@
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void soc_add_fixed_mmio_resources(struct device *dev, int *index)
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{
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static const struct sa_mmio_descriptor soc_fixed_resources[] = {
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{ PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH,
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"PCIEXBAR" },
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{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
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{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
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{ EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
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{ REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },
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{ EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
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/* first field (sa_mmio_descriptor.index) is not used, setting to 0: */
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{ 0, CRAB_ABORT_BASE_ADDR, CRAB_ABORT_SIZE, "CRAB_ABORT" },
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{ 0, TPM_BASE_ADDRESS, TPM_SIZE, "TPM" },
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{ 0, LT_SECURITY_BASE_ADDR, LT_SECURITY_SIZE, "LT_SECURITY" },
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{ 0, IO_APIC_ADDR, APIC_SIZE, "APIC" },
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// PCH_PRESERVERD covers:
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// TraceHub SW BAR, SBREG, PMC MBAR, SPI BAR0, SerialIo BAR in ACPI mode
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// eSPI LGMR BAR, eSPI2 SEGMR BAR, TraceHub MTB BAR, TraceHub FW BAR
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// see fsp/ClientOneSiliconPkg/Fru/AdlPch/Include/PchReservedResourcesAdpP.h
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{ 0, PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE, "PCH_RESERVED" },
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};
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sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
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@ -45,6 +59,83 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index)
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ARRAY_SIZE(soc_vtd_resources));
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}
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/*
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* set MMIO resource's fields
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*/
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static void set_mmio_resource(
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struct sa_mmio_descriptor *resource,
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uint64_t base,
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uint64_t size,
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const char *description)
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{
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if (resource == NULL) {
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printk(BIOS_ERR, "%s: argument resource is NULL for %s\n",
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__func__, description);
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return;
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}
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resource->base = base;
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resource->size = size;
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resource->description = description;
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}
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/*
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* SoC implementation
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*
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* Add all known configurable memory ranges for Host Controller/Memory
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* controller.
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*/
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void soc_add_configurable_mmio_resources(struct device *dev, int *resource_cnt)
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{
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uint64_t size, base, tseg_base;
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int count = 0;
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struct sa_mmio_descriptor cfg_rsrc[6]; /* Increase size when adding more resources */
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/* MMCONF */
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size = get_mmcfg_size(dev);
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if (size > 0)
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set_mmio_resource(&(cfg_rsrc[count++]), CONFIG_ECAM_MMCONF_BASE_ADDRESS,
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size, "MMCONF");
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/* DSM */
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size = get_dsm_size(dev);
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if (size > 0) {
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base = pci_read_config32(dev, DSM_BASE_ADDR_REG) & 0xFFF00000;
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set_mmio_resource(&(cfg_rsrc[count++]), base, size, "DSM");
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}
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/* TSEG */
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size = sa_get_tseg_size();
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tseg_base = sa_get_tseg_base();
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if (size > 0)
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set_mmio_resource(&(cfg_rsrc[count++]), tseg_base, size, "TSEG");
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/* PMRR */
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size = get_valid_prmrr_size();
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if (size > 0) {
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uint64_t mask = pci_read_config32(dev, MSR_PRMRR_PHYS_MASK);
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base = pci_read_config32(dev, MSR_PRMRR_PHYS_BASE) & mask;
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set_mmio_resource(&(cfg_rsrc[count++]), base, size, "PMRR");
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}
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/* GSM */
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size = get_gsm_size(dev);
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if (size > 0) {
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base = sa_get_gsm_base();
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set_mmio_resource(&(cfg_rsrc[count++]), base, size, "GSM");
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}
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/* DPR */
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size = get_dpr_size(dev);
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if (size > 0) {
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/* DPR just below TSEG: */
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base = tseg_base - size;
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set_mmio_resource(&(cfg_rsrc[count++]), base, size, "DPR");
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}
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/* Add all the above */
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sa_add_fixed_mmio_resources(dev, resource_cnt, cfg_rsrc, count);
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}
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/*
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* SoC implementation
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*
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@ -101,3 +192,116 @@ uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz)
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return 65536;
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}
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}
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uint64_t get_mmcfg_size(struct device *dev)
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{
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uint32_t pciexbar_reg;
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uint64_t mmcfg_length;
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if (!dev) {
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printk(BIOS_DEBUG, "%s : device is null\n", __func__);
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return 0;
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}
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pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
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if (!(pciexbar_reg & (1 << 0))) {
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printk(BIOS_DEBUG, "%s : PCIEXBAR disabled\n", __func__);
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return 0;
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}
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switch ((pciexbar_reg & MASK_PCIEXBAR_LENGTH) >> PCIEXBAR_LENGTH_LSB) {
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case PCIEXBAR_LENGTH_4096MB:
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mmcfg_length = 4 * ((uint64_t)GiB);
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break;
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case PCIEXBAR_LENGTH_2048MB:
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mmcfg_length = 2 * ((uint64_t)GiB);
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break;
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case PCIEXBAR_LENGTH_1024MB:
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mmcfg_length = 1 * GiB;
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break;
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case PCIEXBAR_LENGTH_512MB:
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mmcfg_length = 512 * MiB;
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break;
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case PCIEXBAR_LENGTH_256MB:
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mmcfg_length = 256 * MiB;
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break;
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case PCIEXBAR_LENGTH_128MB:
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mmcfg_length = 128 * MiB;
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break;
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case PCIEXBAR_LENGTH_64MB:
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mmcfg_length = 64 * MiB;
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break;
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default:
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printk(BIOS_DEBUG, "%s : PCIEXBAR - invalid length (0x%x)\n", __func__,
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pciexbar_reg & MASK_PCIEXBAR_LENGTH);
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mmcfg_length = 0x0;
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break;
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}
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return mmcfg_length;
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}
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uint64_t get_dsm_size(struct device *dev)
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{
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// - size : B0/D0/F0:R 50h [15:8]
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uint32_t reg32 = pci_read_config32(dev, GGC);
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uint64_t size;
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uint32_t size_field = (reg32 & MASK_DSM_LENGTH) >> MASK_DSM_LENGTH_LSB;
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if (size_field <= 0x10) { // 0x0 - 0x10
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size = size_field * 32 * MiB;
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} else if ((size_field >= 0xF0) && (size_field >= 0xFE)) {
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size = (size_field - 0xEF) * 4 * MiB;
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} else {
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switch (size_field) {
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case 0x20:
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size = 1 * GiB;
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break;
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case 0x30:
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size = 1536 * MiB;
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break;
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case 0x40:
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size = 2 * (uint64_t)GiB;
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break;
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default:
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printk(BIOS_DEBUG, "%s : DSM - invalid length (0x%x)\n",
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__func__, size_field);
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size = 0x0;
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break;
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}
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}
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return size;
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}
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uint64_t get_gsm_size(struct device *dev)
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{
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const u32 gsm_size = pci_read_config32(dev, GGC);
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uint64_t size;
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uint32_t size_field = (gsm_size & MASK_GSM_LENGTH) >> MASK_GSM_LENGTH_LSB;
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switch (size_field) {
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case 0x0:
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size = 0;
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break;
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case 0x1:
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size = 2 * MiB;
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break;
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case 0x2:
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size = 4 * MiB;
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break;
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case 0x3:
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size = 8 * MiB;
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break;
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default:
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size = 0;
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break;
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}
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return size;
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}
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uint64_t get_dpr_size(struct device *dev)
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{
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uint64_t size;
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uint32_t dpr_reg = pci_read_config32(dev, DPR_REG);
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uint32_t size_field = (dpr_reg & MASK_DPR_LENGTH) >> MASK_DPR_LENGTH_LSB;
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size = size_field * MiB;
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return size;
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}
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