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tegra132: adjust vboot2 memlayout to make coreboot compile

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romstage didn't fit in it's region anymore.

Change-Id: I5a2f41cb0e0a87339dbf61906ee2060e132cc394
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10759
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Stefan Reinauer 2015-07-01 13:55:10 -07:00
parent 0232549621
commit ca7794854c
1 changed files with 3 additions and 3 deletions
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6
src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
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@ -36,9 +36,9 @@ SECTIONS
PRERAM_CBFS_CACHE(0x40002000, 72K) PRERAM_CBFS_CACHE(0x40002000, 72K)
VBOOT2_WORK(0x40014000, 16K) VBOOT2_WORK(0x40014000, 16K)
STACK(0x40018000, 2K) STACK(0x40018000, 2K)
BOOTBLOCK(0x40019000, 24K) BOOTBLOCK(0x40019000, 22K)
VERSTAGE(0x4001f000, 60K) VERSTAGE(0x4001e800, 58K)
ROMSTAGE(0x4002e000, 72K) ROMSTAGE(0x4002d000, 76K)
SRAM_END(0x40040000) SRAM_END(0x40040000)
DRAM_START(0x80000000) DRAM_START(0x80000000)