From ca892fe44b287df429215796f85e197f8bf0a968 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 9 May 2020 14:46:09 -0700 Subject: [PATCH] soc/amd/common/block/lpc: Set LPC_IO_PORT_DECODE_ENABLE to 0 when disabling decodes This change sets LPC_IO_PORT_DECODE_ENABLE to 0 as part of lpc_disable_decodes() to ensure that the I/O port decodes are also disabled. Signed-off-by: Furquan Shaikh Change-Id: I1474f561997f2ee1231bd0fcaab4d4d4e98ff923 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41251 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Aaron Durbin --- src/soc/amd/common/block/lpc/lpc_util.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c index c9786e7aa2..2c47a8549a 100644 --- a/src/soc/amd/common/block/lpc/lpc_util.c +++ b/src/soc/amd/common/block/lpc/lpc_util.c @@ -182,6 +182,7 @@ void lpc_disable_decodes(void) reg = pci_read_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE); reg &= LPC_SYNC_TIMEOUT_COUNT_MASK | LPC_SYNC_TIMEOUT_COUNT_ENABLE; pci_write_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, reg); + pci_write_config32(_LPCB_DEV, LPC_IO_PORT_DECODE_ENABLE, 0); /* D14F3x48 enables ranges configured in additional registers */ pci_write_config32(_LPCB_DEV, LPC_MEM_PORT1, 0);