diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 21107aa48b..11733bd05e 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -89,9 +89,10 @@ config X86_RESET_VECTOR
 config RESET_VECTOR_IN_RAM
 	bool
 	depends on ARCH_X86
+	select NO_XIP_EARLY_STAGES
 	help
-	  Select this option if the x86 soc implements custom code to handle the
-	  reset vector in RAM instead of the traditional 0xfffffff0 location.
+	  Select this option if the x86 processor's reset vector is in
+	  preinitialized DRAM instead of the traditional 0xfffffff0 location.
 
 # Aligns 16bit entry code in bootblock so that hyper-threading CPUs
 # can boot AP CPUs to enable their shared caches.
@@ -206,6 +207,7 @@ config VERSTAGE_ADDR
 config POSTCAR_STAGE
 	def_bool y
 	depends on ARCH_X86
+	depends on !RESET_VECTOR_IN_RAM
 
 config VERSTAGE_DEBUG_SPINLOOP
 	bool
diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S
index f36e7dab4d..59b34c8713 100644
--- a/src/arch/x86/assembly_entry.S
+++ b/src/arch/x86/assembly_entry.S
@@ -9,6 +9,13 @@
  * continue with C code execution one needs to set stack pointer and
  * clear .bss variables that are stage specific.
  */
+
+#if CONFIG(RESET_VECTOR_IN_RAM)
+	#define _STACK_TOP _eearlyram_stack
+#else
+	#define _STACK_TOP _ecar_stack
+#endif
+
 .section ".text._start", "ax", @progbits
 .global _start
 _start:
@@ -16,8 +23,8 @@ _start:
 	/* Migrate GDT to this text segment */
 	call	gdt_init
 
-	/* reset stack pointer to CAR stack */
-	mov	$_ecar_stack, %esp
+	/* reset stack pointer to CAR/EARLYRAM stack */
+	mov	$_STACK_TOP, %esp
 
 	/* clear .bss section as it is not shared */
 	cld
diff --git a/src/arch/x86/early_ram.ld b/src/arch/x86/early_ram.ld
new file mode 100644
index 0000000000..941c385b04
--- /dev/null
+++ b/src/arch/x86/early_ram.ld
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+/* This file is included inside a SECTIONS block */
+
+_STACK_SIZE = CONFIG_EARLYRAM_BSP_STACK_SIZE;
+_ = ASSERT(_STACK_SIZE > 0x0, "EARLYRAM_BSP_STACK_SIZE is not configured");
+
+_CONSOLE_SIZE = CONFIG_PRERAM_CBMEM_CONSOLE_SIZE;
+_ = ASSERT(_CONSOLE_SIZE > 0x0, "PRERAM_CBMEM_CONSOLE_SIZE is not configured");
+
+_TIMESTAMPS_SIZE = 0x200;
+#if !CONFIG(NO_FMAP_CACHE)
+_FMAP_SIZE = FMAP_SIZE;
+#else
+_FMAP_SIZE = 0;
+#endif
+
+/*
+ * The PRERAM_CBMEM_CONSOLE, TIMESTAMP, and FMAP_CACHE regions are shared
+ * between the pre-ram stages (bootblock, romstage, etc). We need to assign a
+ * fixed size and consistent link address so they can be shared between stages.
+ *
+ * The stack area is not shared between stages, but is defined here for
+ * convenience.
+ */
+. = CONFIG_X86_RESET_VECTOR - ARCH_STACK_ALIGN_SIZE - _STACK_SIZE - _CONSOLE_SIZE - _TIMESTAMPS_SIZE - _FMAP_SIZE;
+
+_ = ASSERT(. > _eprogram, "Not enough room for .earlyram.data. Try increasing C_ENV_BOOTBLOCK_SIZE, or decreasing either EARLYRAM_BSP_STACK_SIZE or PRERAM_CBMEM_CONSOLE_SIZE.");
+
+.stack ALIGN(ARCH_STACK_ALIGN_SIZE) (NOLOAD) : {
+	EARLYRAM_STACK(., _STACK_SIZE)
+}
+
+.persistent ALIGN(ARCH_POINTER_ALIGN_SIZE) (NOLOAD) : {
+	PRERAM_CBMEM_CONSOLE(., _CONSOLE_SIZE)
+	TIMESTAMP(., _TIMESTAMPS_SIZE)
+	#if !CONFIG(NO_FMAP_CACHE)
+		FMAP_CACHE(., FMAP_SIZE)
+	#endif
+}
+
+_ = ASSERT(. <= CONFIG_X86_RESET_VECTOR, "Earlyram data regions don't fit below the reset vector!");
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
index 2eea83faaf..34d1bd2567 100644
--- a/src/arch/x86/include/arch/memlayout.h
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -8,4 +8,7 @@
 # error "CONFIG_RAMTOP not configured"
 #endif
 
+/* Intel386 psABI requires a 16 byte aligned stack. */
+#define ARCH_STACK_ALIGN_SIZE 16
+
 #endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld
index 5e1ef24655..31767b3c31 100644
--- a/src/arch/x86/memlayout.ld
+++ b/src/arch/x86/memlayout.ld
@@ -9,7 +9,7 @@
 #if ENV_CACHE_AS_RAM
 #define EARLY_MEMLAYOUT	"car.ld"
 #else
-#error "Early DRAM environment for x86 is work-in-progress. */
+#define EARLY_MEMLAYOUT	"early_ram.ld"
 #endif
 #endif
 
@@ -53,7 +53,9 @@ SECTIONS
 /* Bootblock specific scripts which provide more SECTION directives. */
 #include <cpu/x86/16bit/entry16.ld>
 #include <cpu/x86/16bit/reset16.ld>
+#if !CONFIG(RESET_VECTOR_IN_RAM)
 #include <arch/x86/id.ld>
+#endif
 #if CONFIG(CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
 #include <cpu/intel/fit/fit.ld>
 #endif
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig
index c1b84f9d44..933e50f227 100644
--- a/src/cpu/Kconfig
+++ b/src/cpu/Kconfig
@@ -15,6 +15,10 @@ config DCACHE_RAM_SIZE
 config DCACHE_BSP_STACK_SIZE
 	hex
 
+config EARLYRAM_BSP_STACK_SIZE
+	depends on RESET_VECTOR_IN_RAM
+	hex
+
 config SMP
 	bool
 	default y if MAX_CPUS != 1
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index bef3637d1e..af277eaf20 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -58,6 +58,9 @@
 #define PRERAM_CBMEM_CONSOLE(addr, size) \
 	REGION(preram_cbmem_console, addr, size, 4)
 
+#define EARLYRAM_STACK(addr, size) \
+	REGION(earlyram_stack, addr, size, ARCH_STACK_ALIGN_SIZE)
+
 /* Use either CBFS_CACHE (unified) or both (PRERAM|POSTRAM)_CBFS_CACHE */
 #define CBFS_CACHE(addr, size) \
 	REGION(cbfs_cache, addr, size, 4) \