soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI ports

Assign the FSP UPDs for HPD and DDC of DDI ports. FSP assumes that all
DDI ports are enabled and hence configures the HPD and CLK for DDI ports.
This patch initializes only the required UPDs to enable display ports.

BUG=b:123907904
TEST=DP devices working correctly.

Change-Id: Ic0c172cd3d087fc8f49b01ab23feffdababf7166
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/mainboard/google/hatch/variants/baseboard/devicetree.cb

@@ -66,6 +66,11 @@ chip soc/intel/cannonlake
 	register "tdp_pl1_override" = "15"
 	register "tdp_pl2_override" = "44"
 	register "Device4Enable" = "1"
+	# Enable eDP device
+	register "DdiPortEdp" = "1"
+	# Enable HPD for DDI ports B/C
+	register "DdiPortBHpd" = "1"
+	register "DdiPortCHpd" = "1"
 
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)"	# Type-C Port 0
 	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)"	# Type-C Port 1

src/mainboard/google/sarien/variants/arcada/devicetree.cb

@@ -41,6 +41,13 @@ chip soc/intel/cannonlake
 	register "SlowSlewRateForGt" = "0"
 	register "SlowSlewRateForSa" = "0"
 	register "SlowSlewRateForFivr" = "0"
+	# Enable eDP device
+	register "DdiPortEdp" = "1"
+	# Enable HPD for DDI ports B/C
+	register "DdiPortBHpd" = "1"
+	register "DdiPortCHpd" = "1"
+	# Enable DDC for DDI port B
+	register "DdiPortBDdc" = "1"
 
 	# VR Settings Configuration for 4 Domains
 	#+----------------+-------+-------+-------+-------+

src/mainboard/google/sarien/variants/sarien/devicetree.cb

@@ -45,6 +45,13 @@ chip soc/intel/cannonlake
 	register "tdp_pl1_override" = "25"
 	register "tdp_pl2_override" = "51"
 	register "Device4Enable" = "1"
+	# Enable eDP device
+	register "DdiPortEdp" = "1"
+	# Enable HPD for DDI ports B/C
+	register "DdiPortBHpd" = "1"
+	register "DdiPortCHpd" = "1"
+	# Enable DDC for DDI port B
+	register "DdiPortBDdc" = "1"
 
 	# VR Settings Configuration for 4 Domains
 	#+----------------+-------+-------+-------+-------+

src/soc/intel/cannonlake/chip.h

@@ -383,6 +383,21 @@ struct soc_intel_cannonlake_config {
 
 	/* SATA Power Optimizer */
 	uint8_t satapwroptimize;
+
+	/* Enable or disable eDP device */
+	uint8_t DdiPortEdp;
+
+	/* Enable or disable HPD of DDI port B/C/D/F */
+	uint8_t DdiPortBHpd;
+	uint8_t DdiPortCHpd;
+	uint8_t DdiPortDHpd;
+	uint8_t DdiPortFHpd;
+
+	/* Enable or disable DDC of DDI port B/C/D/F  */
+	uint8_t DdiPortBDdc;
+	uint8_t DdiPortCDdc;
+	uint8_t DdiPortDDdc;
+	uint8_t DdiPortFDdc;
 };
 
 typedef struct soc_intel_cannonlake_config config_t;

src/soc/intel/cannonlake/fsp_params.c

@@ -177,6 +177,21 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	params->PchHdaAudioLinkSndw3 = config->PchHdaAudioLinkSndw3;
 	params->PchHdaAudioLinkSndw4 = config->PchHdaAudioLinkSndw4;
 
+	/* eDP device */
+	params->DdiPortEdp = config->DdiPortEdp;
+
+	/* HPD of DDI ports */
+	params->DdiPortBHpd = config->DdiPortBHpd;
+	params->DdiPortCHpd = config->DdiPortCHpd;
+	params->DdiPortDHpd = config->DdiPortDHpd;
+	params->DdiPortFHpd = config->DdiPortFHpd;
+
+	/* DDC of DDI ports */
+	params->DdiPortBDdc = config->DdiPortBDdc;
+	params->DdiPortCDdc = config->DdiPortCDdc;
+	params->DdiPortDDdc = config->DdiPortDDdc;
+	params->DdiPortFDdc = config->DdiPortFDdc;
+
 	/* S0ix */
 	params->PchPmSlpS0Enable = config->s0ix_enable;