soc/intel/alderlake: Hook up CsPiStartHighinEct UPD
This commit provides option for board to set CsPiStartHighinEct FSP UPD using a new cs_pi_start_high_in_ect mb_cfg field. BUG=b:279835630 BRANCH=none TEST=CsPiStartHighinEct UPD is set properly Change-Id: I7d0d5f3c782e29fb047ea421e1a5fdfc30bcc26d Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
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@ -107,6 +107,10 @@ struct mb_cfg {
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/* Enable/Disable TxDqDqs Retraining for Lp4/Lp5/DDR */
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/* Enable/Disable TxDqDqs Retraining for Lp4/Lp5/DDR */
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uint8_t LpDdrDqDqsReTraining;
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uint8_t LpDdrDqDqsReTraining;
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/* Enable/Disable Cs Pi Start with High value in Ect */
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uint8_t cs_pi_start_high_in_ect;
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};
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};
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void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
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void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
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@ -240,6 +240,9 @@ void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
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bool dq_dqs_auto_detect = false;
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bool dq_dqs_auto_detect = false;
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FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig;
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FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig;
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#if CONFIG(SOC_INTEL_RAPTORLAKE)
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mem_cfg->CsPiStartHighinEct = mb_cfg->cs_pi_start_high_in_ect;
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#endif
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mem_cfg->ECT = mb_cfg->ect;
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mem_cfg->ECT = mb_cfg->ect;
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mem_cfg->UserBd = mb_cfg->UserBd;
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mem_cfg->UserBd = mb_cfg->UserBd;
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set_rcomp_config(mem_cfg, mb_cfg);
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set_rcomp_config(mem_cfg, mb_cfg);
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