armv7/exynos5420: Revise SPI open/close/reset procedure.
The original Exynos SPI open/close procedure was copied from U-Boot SPL with some assumptions that only works in SPL stage. For example, it tries to always work in 4-byte transmission mode with only RX data is swapped, and claims a packet for initial address command (and with incorrect size). This commit revises open/close and reset so only the required SPI registers are configured. Change-Id: Ieba1f03d80a8949c39a6658218831ded39853744 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3712 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -102,6 +102,26 @@ void spi_cs_deactivate(struct spi_slave *slave)
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setbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT);
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}
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static inline void exynos_spi_soft_reset(struct exynos_spi *regs)
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{
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/* The soft reset clears only FIFO and status register.
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* All special function registers are not changed. */
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setbits_le32(®s->ch_cfg, SPI_CH_RST);
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clrbits_le32(®s->ch_cfg, SPI_CH_RST);
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}
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static inline void exynos_spi_flush_fifo(struct exynos_spi *regs)
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{
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/*
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* Flush spi tx, rx fifos and reset the SPI controller
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* and clear rx/tx channel
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*/
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clrbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
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clrbits_le32(®s->ch_cfg, SPI_CH_HS_EN);
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exynos_spi_soft_reset(regs);
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setbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
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}
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static void exynos_spi_rx_tx(struct exynos_spi *regs, int todo,
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void *dinp, void const *doutp, int i)
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{
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@ -114,8 +134,7 @@ static void exynos_spi_rx_tx(struct exynos_spi *regs, int todo,
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ASSERT(todo % 4 == 0);
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out_bytes = in_bytes = todo;
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setbits_le32(®s->ch_cfg, SPI_CH_RST);
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clrbits_le32(®s->ch_cfg, SPI_CH_RST);
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exynos_spi_soft_reset(regs);
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writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, ®s->pkt_cnt);
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while (in_bytes) {
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@ -143,35 +162,27 @@ static void exynos_spi_rx_tx(struct exynos_spi *regs, int todo,
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}
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}
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/* set up SPI channel */
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct exynos_spi_slave *espi = to_exynos_spi(slave);
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struct exynos_spi *regs = espi->regs;
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/* set the spi1 GPIO */
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exynos_spi_flush_fifo(regs);
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/* set pktcnt and enable it */
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writel(4 | SPI_PACKET_CNT_EN, ®s->pkt_cnt);
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/* set FB_CLK_SEL */
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// Select Active High Clock, Format A (SCP 30.2.1.8).
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clrbits_le32(®s->ch_cfg, SPI_CH_CPOL_L | SPI_CH_CPHA_B);
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// Set FeedBack Clock Selection.
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writel(SPI_FB_DELAY_180, ®s->fb_clk);
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/* set CH_WIDTH and BUS_WIDTH as word */
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setbits_le32(®s->mode_cfg,
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SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD);
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clrbits_le32(®s->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */
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/* clear rx and tx channel if set priveously */
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clrbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
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setbits_le32(®s->swap_cfg,
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SPI_RX_SWAP_EN | SPI_RX_BYTE_SWAP | SPI_RX_HWORD_SWAP);
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/* do a soft reset */
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setbits_le32(®s->ch_cfg, SPI_CH_RST);
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clrbits_le32(®s->ch_cfg, SPI_CH_RST);
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/* now set rx and tx channel ON */
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setbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN);
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// HIGH speed is required for Tx/Rx to work in 50MHz (SCP 30.2.1.6).
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if (espi->half_duplex) {
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clrbits_le32(®s->ch_cfg, SPI_CH_HS_EN);
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printk(BIOS_DEBUG, "%s: LOW speed.\n", __func__);
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} else {
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setbits_le32(®s->ch_cfg, SPI_CH_HS_EN);
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printk(BIOS_DEBUG, "%s: HIGH speed.\n", __func__);
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}
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return 0;
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}
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@ -209,21 +220,12 @@ static int exynos_spi_read(struct spi_slave *slave, void *dest, uint32_t len,
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void spi_release_bus(struct spi_slave *slave)
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{
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struct exynos_spi *regs = to_exynos_spi(slave)->regs;
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/*
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* Let put controller mode to BYTE as
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* SPI driver does not support WORD mode yet
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*/
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clrbits_le32(®s->mode_cfg,
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SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD);
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/* Reset swap mode to make sure no one relying on default values (Ex,
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* payload or kernel) will go wrong. */
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clrbits_le32(®s->mode_cfg, (SPI_MODE_CH_WIDTH_WORD |
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SPI_MODE_BUS_WIDTH_WORD));
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writel(0, ®s->swap_cfg);
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/*
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* Flush spi tx, rx fifos and reset the SPI controller
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* and clear rx/tx channel
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*/
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clrsetbits_le32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
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clrbits_le32(®s->ch_cfg, SPI_CH_RST);
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clrbits_le32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
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exynos_spi_flush_fifo(regs);
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}
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// SPI as CBFS media.
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