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mainboard/amd/serengeti_cheetah*: Use C89 comments style & remove commented code 

Change-Id: I2fae9e02e2fccaff97f2441fd17f8960e8ab9786
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16975
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Elyes HAOUAS 2016-10-10 21:25:17 +02:00 committed by Martin Roth
parent 15622ee5f0
commit caccd97d4e
14 changed files with 138 additions and 217 deletions
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16
src/mainboard/amd/serengeti_cheetah/acpi_tables.c
View File

@ -80,7 +80,7 @@ unsigned long acpi_fill_madt(unsigned long current)
for(i = 1; i< sysconf.hc_possible_num; i++) {
u32 d = 0;
if(!(sysconf.pci1234[i] & 0x1) ) continue;
// 8131 need to use +4
/* 8131 need to use +4 */
switch (sysconf.hcid[i]) {
case 1:
d = 7;
@ -141,15 +141,15 @@ unsigned long mainboard_write_acpi_tables(device_t dev, unsigned long start, acp
int i;
get_bus_conf(); //it will get sblk, pci1234, hcdn, and sbdn
get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
/* Align ACPI tables to 16 bytes */
start = ALIGN(start, 16);
current = start;
//same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table
/* same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table */
for(i = 1; i < sysconf.hc_possible_num; i++) { // 0: is hc sblink
for(i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */
const char *file_name;
if((sysconf.pci1234[i] & 1) != 1 ) continue;
u8 c;
@ -160,16 +160,16 @@ unsigned long mainboard_write_acpi_tables(device_t dev, unsigned long start, acp
c = (u8) ('A' + i - 1 - 6);
}
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); //pci0 and pci1 are in dsdt
printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); /* pci0 and pci1 are in dsdt */
ssdtx = (acpi_header_t *)current;
switch(sysconf.hcid[i]) {
case 1: //8132
case 1: /* 8132 */
file_name = CONFIG_CBFS_PREFIX "/ssdt2.aml";
break;
case 2: //8151
case 2: /* 8151 */
file_name = CONFIG_CBFS_PREFIX "/ssdt3.aml";
break;
case 3: //8131
case 3: /* 8131 */
file_name = CONFIG_CBFS_PREFIX "/ssdt4.aml";
break;
default:

14
src/mainboard/amd/serengeti_cheetah/fadt.c
View File

@ -41,11 +41,11 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
fadt->firmware_ctrl=(u32)facs;
fadt->dsdt= (u32)dsdt;
// 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server
/* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */
fadt->preferred_pm_profile = 0x03;
fadt->sci_int = 9;
// disable system management mode by setting to 0:
fadt->smi_cmd = 0;//pm_base+0x2f;
/* disable system management mode by setting to 0: */
fadt->smi_cmd = 0;/* pm_base+0x2f */
fadt->acpi_enable = 0xf0;
fadt->acpi_disable = 0xf1;
fadt->s4bios_req = 0x0;
@ -75,10 +75,10 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
fadt->flush_stride = 0;
fadt->duty_offset = 1;
fadt->duty_width = 3;
fadt->day_alrm = 0; // 0x7d these have to be
fadt->mon_alrm = 0; // 0x7e added to cmos.layout
fadt->century = 0; // 0x7f to make rtc alrm work
fadt->iapc_boot_arch = 0x3; // See table 5-11
fadt->day_alrm = 0; /* 0x7d these have to be */
fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
fadt->century = 0; /* 0x7f to make rtc alrm work */
fadt->iapc_boot_arch = 0x3; /* See table 5-11 */
fadt->flags = 0x25;
fadt->res2 = 0;

44
src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
View File

@ -23,30 +23,18 @@
#include <stdlib.h>
#include "mb_sysconf.h"
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
/* Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables */
struct mb_sysconf_t mb_sysconf;
static unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not
//You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
static unsigned pci1234x[] = { /*Here you only need to set value in pci1234 for HT-IO that could be installed or not */
/* You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail */
0x0000ff0,
0x0000ff0,
// 0x0000ff0,
// 0x0000ff0,
// 0x0000ff0,
// 0x0000ff0,
// 0x0000ff0,
// 0x0000ff0
};
static unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
static unsigned hcdnx[] = { /* HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most */
0x20202020,
0x20202020,
// 0x20202020,
// 0x20202020,
// 0x20202020,
// 0x20202020,
// 0x20202020,
// 0x20202020,
};
static unsigned get_bus_conf_done = 0;
@ -64,20 +52,20 @@ static unsigned get_hcid(unsigned i)
dev = dev_find_slot(busn, PCI_DEVFN(devn, 0));
switch (dev->device) {
case 0x7458: //8132
case 0x7458: /*8132 */
id = 1;
break;
case 0x7454: //8151
case 0x7454: /*8151 */
id = 2;
break;
case 0x7450: //8131
case 0x7450: /*8131 */
id = 3;
break;
}
// we may need more way to find out hcid: subsystem id? GPIO read ?
/* we may need more way to find out hcid: subsystem id? GPIO read ? */
// we need use id for 1. bus num, 2. mptable, 3. ACPI table
/* we need use id for 1. bus num, 2. mptable, 3. ACPI table */
return id;
}
@ -92,7 +80,7 @@ void get_bus_conf(void)
struct mb_sysconf_t *m;
if (get_bus_conf_done == 1)
return; //do it only once
return; /* do it only once */
get_bus_conf_done = 1;
@ -150,13 +138,13 @@ void get_bus_conf(void)
if (!(sysconf.pci1234[i] & 0x1))
continue;
// check hcid type here
/* check hcid type here */
sysconf.hcid[i] = get_hcid(i);
switch (sysconf.hcid[i]) {
case 1: //8132
case 3: //8131
case 1: /* 8132 */
case 3: /* 8131 */
m->bus_8132a[j][0] = (sysconf.pci1234[i] >> 16) & 0xff;
@ -190,7 +178,7 @@ void get_bus_conf(void)
break;
case 2: //8151
case 2: /* 8151 */
m->bus_8151[j][0] = (sysconf.pci1234[i] >> 16) & 0xff;
m->sbdn5[j] = sysconf.hcdn[i] & 0xff;
@ -202,7 +190,6 @@ void get_bus_conf(void)
if (dev) {
m->bus_8151[j][1] =
pci_read_config8(dev, PCI_SECONDARY_BUS);
// printk(BIOS_DEBUG, "bus_8151_1=%d\n",bus_8151[j][1]);
} else {
printk(BIOS_DEBUG,
"ERROR - could not find PCI %02x:%02x.0, using defaults\n",
@ -215,7 +202,7 @@ void get_bus_conf(void)
j++;
}
/*I/O APICs: APIC ID Version State Address*/
/* I/O APICs: APIC ID Version State Address */
if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
apicid_base = get_apicid_base(3);
else
@ -227,5 +214,4 @@ void get_bus_conf(void)
m->apicid_8132a[i][0] = apicid_base + 3 + i * 2;
m->apicid_8132a[i][1] = apicid_base + 3 + i * 2 + 1;
}
}

9
src/mainboard/amd/serengeti_cheetah/irq_tables.c
View File

@ -55,7 +55,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
struct mb_sysconf_t *m;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
m = sysconf.mb;
@ -105,7 +105,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
}
}
//pci bridge
/* pci bridge */
printk(BIOS_DEBUG, "setting Onboard AMD Southbridge\n");
static const unsigned char slotIrqs_1_4[4] = { 3, 5, 10, 11 };
pci_assign_irqs(m->bus_8111_0, sysconf.sbdn + 1, slotIrqs_1_4);
@ -123,9 +123,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq_info++;
slot_num++;
//pcix bridge
// write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3 << 3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
// pirq_info++; slot_num++;
/* pcix bridge */
int j = 0;
@ -157,5 +155,4 @@ unsigned long write_pirq_routing_table(unsigned long addr)
printk(BIOS_INFO, "done.\n");
return (unsigned long)pirq_info;
}

38
src/mainboard/amd/serengeti_cheetah/mptable.c
View File

@ -41,8 +41,8 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); //8111
/* I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); /* 8111 */
{
device_t dev;
struct resource *res;
@ -69,8 +69,8 @@ static void *smp_write_config_table(void *v)
if(!(sysconf.pci1234[i] & 0x1) ) continue;
switch(sysconf.hcid[i]) {
case 1: // 8132
case 3: // 8131
case 1: /* 8132 */
case 3: /* 8131 */
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
@ -97,33 +97,33 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0);
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
//??? What
/* ??? What */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
// Onboard AMD USB
/* Onboard AMD USB */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0 << 2)|3, m->apicid_8111, 0x13);
//Slot 3 PCI 32
/*Slot 3 PCI 32 */
for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); /* 16 */
}
//Slot 4 PCI 32
/* Slot 4 PCI 32 */
for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); /* 16 */
}
//Slot 1 PCI-X 133/100/66
/* Slot 1 PCI-X 133/100/66 */
for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4); //
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4);
}
//Slot 2 PCI-X 133/100/66
/* Slot 2 PCI-X 133/100/66 */
for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); //25
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); /* 25 */
}
j = 0;
@ -140,9 +140,9 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
//Slot 1 PCI-X 133/100/66
/* Slot 1 PCI-X 133/100/66 */
for(ii = 0; ii < 4; ii++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0 << 2)|ii, m->apicid_8132a[j][0], (0+ii)%4); //
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0 << 2)|ii, m->apicid_8132a[j][0], (0+ii)%4);
}
}
}
@ -151,9 +151,9 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
//Slot 2 PCI-X 133/100/66
/* Slot 2 PCI-X 133/100/66 */
for(ii = 0; ii < 4; ii++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0 << 2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0 << 2)|ii, m->apicid_8132a[j][1], (0+ii)%4); /* 25 */
}
}
}
@ -161,7 +161,7 @@ static void *smp_write_config_table(void *v)
break;
case 2:
// Slot AGP
/* Slot AGP */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11);
break;
}

4
src/mainboard/amd/serengeti_cheetah/resourcemap.c
View File

@ -260,8 +260,8 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration regin i
*/
PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x08070013, // AMD 8151 on link0 of CPU 1
PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06000003, /* AMD 8111 on link0 of CPU 0 */
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x08070013, /* AMD 8151 on link0 of CPU 1 */
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
};

64
src/mainboard/amd/serengeti_cheetah/romstage.c
View File

@ -37,8 +37,8 @@
static void memreset_setup(void)
{
//GPIO on amd8111 to enable MEMRST ????
outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN = 1
/* GPIO on amd8111 to enable MEMRST ???? */
outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); /* REVC_MEMRST_EN = 1 */
outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17);
}
@ -49,7 +49,7 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl)
#define SMBUS_HUB 0x18
int ret,i;
unsigned device=(ctrl->channel0[0])>>8;
/* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/
/* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time */
i = 2;
do {
ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
@ -82,19 +82,19 @@ static inline int spd_read_byte(unsigned device, unsigned address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
//first node
/* first node */
RC0|DIMM0, RC0|DIMM2, 0, 0,
RC0|DIMM1, RC0|DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
//second node
/* second node */
RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 2
// third node
/* third node */
RC2|DIMM0, RC2|DIMM2, 0, 0,
RC2|DIMM1, RC2|DIMM3, 0, 0,
// four node
/* four node */
RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6,
RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7,
#endif
@ -114,27 +114,21 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
setup_mb_resource_map();
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 0));
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
setup_coherent_ht_domain(); // routing table and start other core0
set_sysinfo_in_ram(0); /* in BSP so could hold all ap until sysinfo is in ram */
setup_coherent_ht_domain(); /* routing table and start other core0 */
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
/* It is said that we should start core1 after all core0 launched */
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
* (there may be apic id conflicts in that case)
@ -144,13 +138,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#endif
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if 0
//it your CPU min fid is 1G, you can change HT to 1G and FID to max one time.
needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
#endif
ht_setup_chains_x(sysinfo); /* it will init sblnk and sbbusn, nodes, sbdn */
#if CONFIG_SET_FIDVID
/* Check to see if processor is capable of changing FIDVID */
@ -169,7 +157,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
// show final fid and vid
/* show final fid and vid */
{
msr_t msr;
msr = rdmsr(0xc0010042);
@ -185,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
// fidvid change will issue one LDTSTOP and the HT change will be effective too
/* fidvid change will issue one LDTSTOP and the HT change will be effective too */
if (needs_reset) {
printk(BIOS_INFO, "ht reset -\n");
soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
@ -193,36 +181,18 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#endif
allow_all_aps_stop(bsp_apicid);
//It's the time to set ctrl in sysinfo now;
/* It's the time to set ctrl in sysinfo now; */
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus();
#if 0
int i;
for(i = 0; i < 4; i++) {
activate_spd_rom(&cpu[i]);
dump_smbus_registers();
}
#endif
memreset_setup();
//do we need apci timer, tsc...., only debug need it for better output
/* do we need apci timer, tsc...., only debug need it for better output */
/* all ap stopped? */
// init_timer(); // Need to use TMICT to synchronize FID/VID
/* Need to use TMICT to synchronize FID/VID */
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
#if 0
print_pci_devices();
#endif
#if 0
// dump_pci_devices();
dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
#endif
post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
post_cache_as_ram(); /* bsp swtich stack to RAM and copy sysinfo RAM now */
}

17
src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c
View File

@ -53,7 +53,6 @@ unsigned long acpi_fill_madt(unsigned long current)
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_1,
res->base, gsi_base );
gsi_base+=7;
}
}
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0] & 0xff)+1, 1));
@ -72,7 +71,7 @@ unsigned long acpi_fill_madt(unsigned long current)
for(i = 1; i < sysconf.hc_possible_num; i++) {
u32 d = 0;
if(!(sysconf.pci1234[i] & 0x1) ) continue;
// 8131 need to use +4
/* 8131 need to use +4 */
switch (sysconf.hcid[i]) {
case 1:
d = 7;
@ -100,7 +99,6 @@ unsigned long acpi_fill_madt(unsigned long current)
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1],
res->base, gsi_base );
gsi_base+=d;
}
}
break;
@ -133,12 +131,13 @@ unsigned long mainboard_write_acpi_tables(device_t device,
int i;
get_bus_conf(); //it will get sblk, pci1234, hcdn, and sbdn
get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
/* same htio, but different possition? We may have to copy,
change HCIN, and recalculate the checknum and add_table */
* change HCIN, and recalculate the checknum and add_table
*/
for(i = 1; i < sysconf.hc_possible_num; i++) { // 0: is hc sblink
for(i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */
const char *file_name;
if((sysconf.pci1234[i] & 1) != 1 ) continue;
u8 c;
@ -149,7 +148,7 @@ unsigned long mainboard_write_acpi_tables(device_t device,
c = (u8) ('A' + i - 1 - 6);
}
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt
printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); /* pci0 and pci1 are in dsdt */
ssdtx = (acpi_header_t *)current;
switch(sysconf.hcid[i]) {
case 1:
@ -158,11 +157,11 @@ unsigned long mainboard_write_acpi_tables(device_t device,
case 2:
file_name = CONFIG_CBFS_PREFIX "/ssdt3.aml";
break;
case 3: //8131
case 3: /* 8131 */
file_name = CONFIG_CBFS_PREFIX "/ssdt4.aml";
break;
default:
//HTX no io apic
/* HTX no io apic */
file_name = CONFIG_CBFS_PREFIX "/ssdt5.aml";
}
p = cbfs_boot_map_with_leak(

27
src/mainboard/amd/serengeti_cheetah_fam10/fadt.c
View File

@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/
/*
* ACPI - create the Fixed ACPI Description Tables (FADT)
*/
@ -44,16 +43,15 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
fadt->firmware_ctrl=(u32)facs;
fadt->dsdt= (u32)dsdt;
// 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server
/* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */
fadt->preferred_pm_profile = 0x03;
fadt->sci_int = 9;
// disable system management mode by setting to 0:
fadt->smi_cmd = 0;//pm_base+0x2f;
/* disable system management mode by setting to 0: */
fadt->smi_cmd = 0;/* pm_base+0x2f */
fadt->acpi_enable = 0xf0;
fadt->acpi_disable = 0xf1;
fadt->s4bios_req = 0x0;
fadt->pstate_cnt = 0x00; // SMM is not used for p-state control
// fadt->pstate_cnt = 0xe2;
fadt->pstate_cnt = 0x00; /* SMM is not used for p-state control */
fadt->pm1a_evt_blk = pm_base;
fadt->pm1b_evt_blk = 0x0000;
@ -72,18 +70,17 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
fadt->gpe1_blk_len = 8;
fadt->gpe1_base = 16;
fadt->cst_cnt = 0x00;// SMM is not used for p-state control
// fadt->cst_cnt = 0xe3;
fadt->cst_cnt = 0x00;/* SMM is not used for p-state control */
fadt->p_lvl2_lat = 101;
fadt->p_lvl3_lat = 1001;
fadt->flush_size = 0;
fadt->flush_stride = 0;
fadt->duty_offset = 1;
fadt->duty_width = 3;
fadt->day_alrm = 0; // 0x7d these have to be
fadt->mon_alrm = 0; // 0x7e added to cmos.layout
fadt->century = 0; // 0x7f to make rtc alrm work
fadt->iapc_boot_arch = 0x3; // See table 5-11
fadt->day_alrm = 0; /* 0x7d these have to be */
fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
fadt->century = 0; /* 0x7f to make rtc alrm work */
fadt->iapc_boot_arch = 0x3; /* See table 5-11 */
fadt->flags = 0x25;
fadt->res2 = 0;
@ -115,7 +112,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
fadt->x_pm1b_evt_blk.addrl = 0x0;
fadt->x_pm1b_evt_blk.addrh = 0x0;
fadt->x_pm1a_cnt_blk.space_id = 1;
fadt->x_pm1a_cnt_blk.bit_width = 16;
fadt->x_pm1a_cnt_blk.bit_offset = 0;
@ -130,7 +126,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
fadt->x_pm1b_cnt_blk.addrl = 0x0;
fadt->x_pm1b_cnt_blk.addrh = 0x0;
fadt->x_pm2_cnt_blk.space_id = 1;
fadt->x_pm2_cnt_blk.bit_width = 0;
fadt->x_pm2_cnt_blk.bit_offset = 0;
@ -138,7 +133,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
fadt->x_pm2_cnt_blk.addrl = 0x0;
fadt->x_pm2_cnt_blk.addrh = 0x0;
fadt->x_pm_tmr_blk.space_id = 1;
fadt->x_pm_tmr_blk.bit_width = 32;
fadt->x_pm_tmr_blk.bit_offset = 0;
@ -146,7 +140,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
fadt->x_pm_tmr_blk.addrl = pm_base+0x08;
fadt->x_pm_tmr_blk.addrh = 0x0;
fadt->x_gpe0_blk.space_id = 1;
fadt->x_gpe0_blk.bit_width = 32;
fadt->x_gpe0_blk.bit_offset = 0;
@ -154,7 +147,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
fadt->x_gpe0_blk.addrl = pm_base+0x20;
fadt->x_gpe0_blk.addrh = 0x0;
fadt->x_gpe1_blk.space_id = 1;
fadt->x_gpe1_blk.bit_width = 64;
fadt->x_gpe1_blk.bit_offset = 16;
@ -163,5 +155,4 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
fadt->x_gpe1_blk.addrh = 0x0;
header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
}

28
src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
View File

@ -29,8 +29,9 @@
struct mb_sysconf_t mb_sysconf;
/* Here you only need to set value in pci1234 for HT-IO that could be
installed or not You may need to preset pci1234 for HTIO board, please
refer to src/northbridge/amd/amdfam10/get_sblk_pci1234.c for detail */
* installed or not You may need to preset pci1234 for HTIO board, please
* refer to src/northbridge/amd/amdfam10/get_sblk_pci1234.c for detail
*/
static u32 pci1234x[] = {
0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc,
0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc,
@ -42,7 +43,8 @@ static u32 pci1234x[] = {
/* HT Chain device num, actually it is unit id base of every ht device
in chain, assume every chain only have 4 ht device at most */
* in chain, assume every chain only have 4 ht device at most
*/
static unsigned hcdnx[] = {
0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
@ -70,18 +72,18 @@ static u32 get_hcid(u32 i)
dev = dev_find_slot(busn, PCI_DEVFN(devn,0));
switch (dev->device) {
case 0x7458: //8132
case 0x7458: /* 8132 */
id = 1;
break;
case 0x7454: //8151
case 0x7454: /* 8151 */
id = 2;
break;
case 0x7450: //8131
case 0x7450: /* 8131 */
id = 3;
break;
}
// we may need more way to find out hcid: subsystem id? GPIO read ?
// we need use id for 1. bus num, 2. mptable, 3. ACPI table
/* we may need more way to find out hcid: subsystem id? GPIO read ? */
/* we need use id for 1. bus num, 2. mptable, 3. ACPI table */
return id;
}
@ -94,7 +96,7 @@ void get_bus_conf(void)
struct mb_sysconf_t *m;
if(get_bus_conf_done == 1)
return; //do it only once
return; /* do it only once */
get_bus_conf_done = 1;
@ -145,13 +147,13 @@ void get_bus_conf(void)
for(i = 1; i< sysconf.hc_possible_num; i++) {
if(!(sysconf.pci1234[i] & 0x1) ) continue;
// check hcid type here
/* check hcid type here */
sysconf.hcid[i] = get_hcid(i);
switch(sysconf.hcid[i]) {
case 1: //8132
case 3: //8131
case 1: /* 8132 */
case 3: /* 8131 */
m->bus_8132a[j][0] = (sysconf.pci1234[i] >> 12) & 0xff;
@ -175,7 +177,7 @@ void get_bus_conf(void)
break;
case 2: //8151
case 2: /* 8151 */
m->bus_8151[j][0] = (sysconf.pci1234[i] >> 12) & 0xff;
m->sbdn5[j] = sysconf.hcdn[i] & 0xff;

9
src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c
View File

@ -54,7 +54,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
struct mb_sysconf_t *m;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
m = sysconf.mb;
@ -86,16 +86,14 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq_info = (void *)(&pirq->checksum + 1);
slot_num = 0;
//pci bridge
/* pci bridge */
write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn + 1) << 3) | 0,
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
0);
pirq_info++;
slot_num++;
//pcix bridge
// write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3 << 3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
// pirq_info++; slot_num++;
/* pcix bridge */
int j = 0;
@ -142,5 +140,4 @@ unsigned long write_pirq_routing_table(unsigned long addr)
printk(BIOS_INFO, "done.\n");
return (unsigned long)pirq_info;
}

34
src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
View File

@ -43,8 +43,8 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); //8111
/* I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); /* 8111 */
{
device_t dev;
struct resource *res;
@ -99,33 +99,33 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0);
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
//??? What
/* ??? What */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
// Onboard AMD USB
/* Onboard AMD USB */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0 << 2)|3, m->apicid_8111, 0x13);
//Slot 3 PCI 32
/* Slot 3 PCI 32 */
for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); /* 16 */
}
// Slot 4 PCI 32
/* Slot 4 PCI 32 */
for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); /* 16 */
}
// Slot 1 PCI-X 133/100/66
/* Slot 1 PCI-X 133/100/66 */
for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4); //
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4);
}
//Slot 2 PCI-X 133/100/66
/* Slot 2 PCI-X 133/100/66 */
for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); //25
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); /* 25 */
}
j = 0;
@ -144,9 +144,9 @@ static void *smp_write_config_table(void *v)
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
for(jj = 0; jj < 4; jj++) {
//Slot 1 PCI-X 133/100/66
/* Slot 1 PCI-X 133/100/66 */
for(ii = 0; ii < 4; ii++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (jj << 2)|ii, m->apicid_8132a[j][0], (jj+ii)%4); //
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (jj << 2)|ii, m->apicid_8132a[j][0], (jj+ii)%4);
}
}
}
@ -157,9 +157,9 @@ static void *smp_write_config_table(void *v)
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
for(jj = 0; jj < 4; jj++) {
//Slot 2 PCI-X 133/100/66
/* Slot 2 PCI-X 133/100/66 */
for(ii = 0; ii < 4; ii++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (jj << 2)|ii, m->apicid_8132a[j][1], (jj+ii)%4); //25
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (jj << 2)|ii, m->apicid_8132a[j][1], (jj+ii)%4); /* 25 */
}
}
}
@ -168,7 +168,7 @@ static void *smp_write_config_table(void *v)
break;
case 2:
// Slot AGP
/* Slot AGP */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11);
break;
}

12
src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c
View File

@ -13,8 +13,6 @@
* GNU General Public License for more details.
*/
static void setup_mb_resource_map(void)
{
static const unsigned int register_values[] = {
@ -45,7 +43,7 @@ static void setup_mb_resource_map(void)
* This field defines the upper address bits of a 40 bit address
* that define the end of the DRAM region.
*/
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10
/* Don't touch it, we need it for CAR with FAM10 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
@ -83,7 +81,7 @@ static void setup_mb_resource_map(void)
* This field defines the upper address bits of a 40-bit address
* that define the start of the DRAM region.
*/
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CAR with FAM10
/* don't touch it, we need it for CAR with FAM10 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
@ -131,7 +129,6 @@ static void setup_mb_resource_map(void)
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers
* F1:0x80 i = 0
@ -166,7 +163,6 @@ static void setup_mb_resource_map(void)
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
/* PCI I/O Limit i Registers
* F1:0xC4 i = 0
@ -193,7 +189,6 @@ static void setup_mb_resource_map(void)
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
@ -223,7 +218,6 @@ static void setup_mb_resource_map(void)
* This field defines the start of PCI I/O region n
* [31:25] Reserved
*/
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
@ -264,7 +258,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration regin i
*/
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
/* AMD 8111 on link0 of CPU 0 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,

39
src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
View File

@ -14,10 +14,8 @@
*/
#define SYSTEM_TYPE 0 /* SERVER */
//#define SYSTEM_TYPE 1 /* DESKTOP */
//#define SYSTEM_TYPE 2 /* MOBILE */
//used by incoherent_ht
/* used by incoherent_ht */
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0
@ -50,8 +48,8 @@
static void memreset_setup(void)
{
//GPIO on amd8111 to enable MEMRST ????
outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); // REVC_MEMRST_EN = 1
/* GPIO on amd8111 to enable MEMRST ???? */
outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); /* REVC_MEMRST_EN = 1 */
outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17);
}
@ -87,16 +85,16 @@ static int spd_read_byte(u32 device, u32 address)
#include "northbridge/amd/amdfam10/early_ht.c"
static const u8 spd_addr[] = {
//first node
/* first node */
RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
//second node
/* second node */
RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 2
// third node
/* third node */
RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
// forth node
/* forth node */
RC03, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 4
@ -208,12 +206,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
// Load MPB
/* Load MPB */
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
@ -268,10 +264,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
if (!warm_reset_detect(0)) { // BSP is node 0
if (!warm_reset_detect(0)) { /* BSP is node 0 */
init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
} else {
init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */
}
post_code(0x3A);
@ -308,8 +304,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
memreset_setup();
post_code(0x40);
// die("Die Before MCT init.");
timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
@ -320,18 +314,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
amdmct_cbmem_store_info(sysinfo);
/*
dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
*/
// die("After MCT init before CAR disabled.");
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */
post_code(0x43); /* Should never see this post code. */
}
/**