diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig
index b9d777cf7b..864e577c3d 100644
--- a/src/mainboard/google/nyan/Kconfig
+++ b/src/mainboard/google/nyan/Kconfig
@@ -25,12 +25,14 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select MAINBOARD_HAS_CHROMEOS
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_SPI
+	select EC_SOFTWARE_SYNC
 	select TEGRA124_MODEL_CD570M
 	select MAINBOARD_HAS_BOOTBLOCK_INIT
 	select MAINBOARD_DO_NATIVE_VGA_INIT
 	select BOARD_ROMSIZE_KB_1024
 	select SPI_FLASH
 	select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B
+	select VIRTUAL_DEV_SWITCH
 
 config MAINBOARD_DIR
 	string
@@ -86,4 +88,20 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS
 	hex
 	default 1
 
+config VBOOT_RAMSTAGE_INDEX
+	hex
+	default 0x2
+
+config FLASHMAP_OFFSET
+	hex
+	default 0x00100000
+
+config DRIVER_TPM_I2C_BUS
+	hex
+	default 0x2
+
+config DRIVER_TPM_I2C_ADDR
+	hex
+	default 0x20
+
 endif # BOARD_GOOGLE_NYAN
diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c
index 7310cc873a..10aeb5466c 100644
--- a/src/mainboard/google/nyan/romstage.c
+++ b/src/mainboard/google/nyan/romstage.c
@@ -26,6 +26,8 @@
 #include <cbfs.h>
 #include <cbmem.h>
 #include <console/console.h>
+#include <romstage_handoff.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 #include "sdram_configs.h"
 #include <soc/nvidia/tegra/i2c.h>
 #include <soc/nvidia/tegra124/chip.h>
@@ -195,11 +197,8 @@ static void __attribute__((noinline)) romstage(void)
 
 	cbmem_initialize_empty();
 
-#if CONFIG_COLLECT_TIMESTAMPS
 	timestamp_init(0);
 	timestamp_add(TS_START_ROMSTAGE, romstage_start_time);
-	timestamp_add(TS_START_COPYRAM, timestamp_get());
-#endif
 
 	// Enable additional peripherals we need for ROM stage.
 	clock_enable_clear_reset(0, CLK_H_SBC1, CLK_U_I2C3, 0, 0, 0);
@@ -209,11 +208,13 @@ static void __attribute__((noinline)) romstage(void)
 	configure_ec_spi_bus();
 	configure_tpm_i2c_bus();
 
+	vboot_verify_firmware(romstage_handoff_find_or_add());
+
+	timestamp_add(TS_START_COPYRAM, timestamp_get());
 	void *entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
 				      "fallback/coreboot_ram");
-#if CONFIG_COLLECT_TIMESTAMPS
 	timestamp_add(TS_END_COPYRAM, timestamp_get());
-#endif
+
 	stage_exit(entry);
 }
 
diff --git a/src/mainboard/google/nyan_big/Kconfig b/src/mainboard/google/nyan_big/Kconfig
index 63643d3f53..16ad98dab4 100644
--- a/src/mainboard/google/nyan_big/Kconfig
+++ b/src/mainboard/google/nyan_big/Kconfig
@@ -25,12 +25,14 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select MAINBOARD_HAS_CHROMEOS
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_SPI
+	select EC_SOFTWARE_SYNC
 	select TEGRA124_MODEL_CD570M
 	select MAINBOARD_HAS_BOOTBLOCK_INIT
 	select MAINBOARD_DO_NATIVE_VGA_INIT
 	select BOARD_ROMSIZE_KB_1024
 	select SPI_FLASH
 	select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B
+	select VIRTUAL_DEV_SWITCH
 
 
 config MAINBOARD_DIR
@@ -87,4 +89,20 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS
 	hex
 	default 1
 
+config VBOOT_RAMSTAGE_INDEX
+	hex
+	default 0x2
+
+config FLASHMAP_OFFSET
+	hex
+	default 0x00100000
+
+config DRIVER_TPM_I2C_BUS
+	hex
+	default 0x2
+
+config DRIVER_TPM_I2C_ADDR
+	hex
+	default 0x20
+
 endif # BOARD_GOOGLE_NYAN_BIG
diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c
index d7cc1bf3a3..c239b4eb7e 100644
--- a/src/mainboard/google/nyan_big/romstage.c
+++ b/src/mainboard/google/nyan_big/romstage.c
@@ -26,6 +26,8 @@
 #include <cbfs.h>
 #include <cbmem.h>
 #include <console/console.h>
+#include <romstage_handoff.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 #include "sdram_configs.h"
 #include <soc/nvidia/tegra/i2c.h>
 #include <soc/nvidia/tegra124/chip.h>
@@ -195,11 +197,8 @@ static void __attribute__((noinline)) romstage(void)
 
 	cbmem_initialize_empty();
 
-#if CONFIG_COLLECT_TIMESTAMPS
 	timestamp_init(0);
 	timestamp_add(TS_START_ROMSTAGE, romstage_start_time);
-	timestamp_add(TS_START_COPYRAM, timestamp_get());
-#endif
 
 	// Enable additional peripherals we need for ROM stage.
 	clock_enable_clear_reset(0, CLK_H_SBC1, CLK_U_I2C3, 0, 0, 0);
@@ -209,11 +208,13 @@ static void __attribute__((noinline)) romstage(void)
 	configure_ec_spi_bus();
 	configure_tpm_i2c_bus();
 
+	vboot_verify_firmware(romstage_handoff_find_or_add());
+
+	timestamp_add(TS_START_COPYRAM, timestamp_get());
 	void *entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
 				      "fallback/coreboot_ram");
-#if CONFIG_COLLECT_TIMESTAMPS
 	timestamp_add(TS_END_COPYRAM, timestamp_get());
-#endif
+
 	stage_exit(entry);
 }
 
diff --git a/src/mainboard/google/nyan_blaze/Kconfig b/src/mainboard/google/nyan_blaze/Kconfig
index 838bb181bd..353abe0c49 100644
--- a/src/mainboard/google/nyan_blaze/Kconfig
+++ b/src/mainboard/google/nyan_blaze/Kconfig
@@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select CHROMEOS
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_SPI
+	select EC_SOFTWARE_SYNC
 	select SOC_NVIDIA_TEGRA124
 	select TEGRA124_MODEL_CD570M
 	select MAINBOARD_HAS_BOOTBLOCK_INIT
@@ -32,6 +33,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select BOARD_ROMSIZE_KB_1024
 	select SPI_FLASH
 	select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B
+	select VIRTUAL_DEV_SWITCH
 
 
 config MAINBOARD_DIR
@@ -88,4 +90,20 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS
 	hex
 	default 1
 
+config VBOOT_RAMSTAGE_INDEX
+	hex
+	default 0x2
+
+config FLASHMAP_OFFSET
+	hex
+	default 0x00100000
+
+config DRIVER_TPM_I2C_BUS
+	hex
+	default 0x2
+
+config DRIVER_TPM_I2C_ADDR
+	hex
+	default 0x20
+
 endif # BOARD_GOOGLE_NYAN_BLAZE
diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c
index d7cc1bf3a3..c239b4eb7e 100644
--- a/src/mainboard/google/nyan_blaze/romstage.c
+++ b/src/mainboard/google/nyan_blaze/romstage.c
@@ -26,6 +26,8 @@
 #include <cbfs.h>
 #include <cbmem.h>
 #include <console/console.h>
+#include <romstage_handoff.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 #include "sdram_configs.h"
 #include <soc/nvidia/tegra/i2c.h>
 #include <soc/nvidia/tegra124/chip.h>
@@ -195,11 +197,8 @@ static void __attribute__((noinline)) romstage(void)
 
 	cbmem_initialize_empty();
 
-#if CONFIG_COLLECT_TIMESTAMPS
 	timestamp_init(0);
 	timestamp_add(TS_START_ROMSTAGE, romstage_start_time);
-	timestamp_add(TS_START_COPYRAM, timestamp_get());
-#endif
 
 	// Enable additional peripherals we need for ROM stage.
 	clock_enable_clear_reset(0, CLK_H_SBC1, CLK_U_I2C3, 0, 0, 0);
@@ -209,11 +208,13 @@ static void __attribute__((noinline)) romstage(void)
 	configure_ec_spi_bus();
 	configure_tpm_i2c_bus();
 
+	vboot_verify_firmware(romstage_handoff_find_or_add());
+
+	timestamp_add(TS_START_COPYRAM, timestamp_get());
 	void *entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
 				      "fallback/coreboot_ram");
-#if CONFIG_COLLECT_TIMESTAMPS
 	timestamp_add(TS_END_COPYRAM, timestamp_get());
-#endif
+
 	stage_exit(entry);
 }