intel/apollolake: Disable setting of EISS bit in FSP

chrome-os-partner:54589

Change-Id: I5bdd417ed2f7ec013aeb8a0d4a9de57b1ad564a1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15276
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/apollolake/chip.c

@@ -138,6 +138,9 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
 	silconfig->P2sbBase = P2SB_BAR;
 
 	silconfig->IshEnable = cfg->integrated_sensor_hub_enable;
+
+	/* Disable setting of EISS bit in FSP. */
+	silconfig->SpiEiss = 0;
 }
 
 struct chip_operations soc_intel_apollolake_ops = {