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mb/google/brya: Adjust FMD file for some boards 

When brya boards that use ChromeOS autoupdate update their firmware,
devices with SOC_INTEL_CSE_SUB_PART_UPDATE will end up attempting to
replace IOM and NPHY BPDT firmware in the CSE region. However, because
of the way the autoupdate works, the CSE RO will not be updated during
autoupdate. This means that these boards now have different stitching
schemes between CSE RO and RW and this causes the sub-partition update
to fail and the boot hangs. To remedy the situation for these boards,
a separate FMD files is provided so they can continue to use the
cse_serger tool for stitching. The only boards affected were kano and
brask, so they are updated here.

BUG=b:218376385
TEST=use flashrom to downgrade to 14474 then use futility to update to
image with this patch and system boots.

Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com>
Change-Id: Ia8bdf6b28d952f6d983b84e39da96e159027a822
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Tracy Wu 2022-02-09 10:34:12 +08:00 committed by Felix Held
parent 8b875d028d
commit cae27ebf49
2 changed files with 64 additions and 0 deletions
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4
src/mainboard/google/brya/Kconfig
View File

@ -120,6 +120,10 @@ config DRIVER_TPM_I2C_ADDR
hex
default 0x50
config FMDFILE
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-serger.fmd" if BOARD_GOOGLE_KANO || BOARD_GOOGLE_BRASK
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd"
config TPM_TIS_ACPI_INTERRUPT
int
default 13 # GPE0_DW0_13 (GPP_A13_IRQ)

60
src/mainboard/google/brya/chromeos-serger.fmd Normal file
View File

@ -0,0 +1,60 @@
FLASH 32M {
SI_ALL 5M {
SI_DESC 4K
SI_ME {
CSE_LAYOUT 8K
CSE_RO 1588K
CSE_DATA 512K
# 64-KiB aligned to optimize RW erases during CSE update.
CSE_RW 3008K
}
}
SI_BIOS 27M {
RW_SECTION_A 8M {
VBLOCK_A 64K
FW_MAIN_A(CBFS)
RW_FWID_A 64
ME_RW_A(CBFS) 3008K
}
RW_LEGACY(CBFS) 2M
RW_MISC 1M {
UNIFIED_MRC_CACHE(PRESERVE) 128K {
RECOVERY_MRC_CACHE 64K
RW_MRC_CACHE 64K
}
RW_ELOG(PRESERVE) 16K
RW_SHARED 16K {
SHARED_DATA 8K
VBLOCK_DEV 8K
}
# The RW_SPD_CACHE region is only used for brya variants that use DDRx memory.
# It is placed in the common `chromeos.fmd` file because it is only 4K and there
# is free space in the RW_MISC region that cannot be easily reclaimed because
# the RW_SECTION_B must start on the 16M boundary.
RW_SPD_CACHE(PRESERVE) 4K
RW_VPD(PRESERVE) 8K
RW_NVRAM(PRESERVE) 24K
}
# This section starts at the 16M boundary in SPI flash.
# ADL does not support a region crossing this boundary,
# because the SPI flash is memory-mapped into two non-
# contiguous windows.
RW_SECTION_B 8M {
VBLOCK_B 64K
FW_MAIN_B(CBFS)
RW_FWID_B 64
ME_RW_B(CBFS) 3008K
}
# Make WP_RO region align with SPI vendor
# memory protected range specification.
WP_RO 8M {
RO_VPD(PRESERVE) 16K
RO_SECTION {
FMAP 2K
RO_FRID 64
GBB@4K 448K
COREBOOT(CBFS)
}
}
}
}