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soc/intel/apollolake: Fix PCI memory resource alloc 

There is a mismatch in how PCI memory resources are allocated on Apollo
Lake with the current configuration. While the ACPI code expects
resources to be below PCR_BASE_ADDRESS (i.e. PMAX), the coreboot C code
allocates them above, leading to the following error messages on Linux:

    pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window]
    pci_bus 0000:00: root bus resource [mem 0x80000000-0xd0000000 window]
    pci_bus 0000:00: root bus resource [mem 0x280000000-0x7fffffffff window]
    pci 0000:00:13.1: can't claim BAR 14 [mem 0xdeb00000-0xdebfffff]: no compatible bridge window
    pci 0000:00:13.1: can't claim BAR 15 [mem 0xdec00000-0xdecfffff 64bit pref]: no compatible bridge window
    pci 0000:00:13.1: BAR 14: assigned [mem 0x80000000-0x800fffff]
    pci 0000:00:13.1: BAR 15: assigned [mem 0x281300000-0x2813fffff 64bit pref]

Tested on up/squared with Linux kernel version 6.1.0.

Fix this by setting the DOMAIN_RESOURCE_32BIT_LIMIT to PCR_BASE_ADDRESS,
and by moving the UART base address into the expected range.

Thanks to Nico Huber for the help in writing this patch.

Change-Id: I3a805beb47ab4d19cf8dfce0942485e7982861b1
Signed-off-by: Reto Buerki <reet@codelabs.ch>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79957
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Reto Buerki 2024-01-11 09:26:55 +01:00 committed by Felix Held
parent 3b5b66d829
commit caf80848bb
1 changed files with 4 additions and 1 deletions
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5
src/soc/intel/apollolake/Kconfig
View File

@ -338,7 +338,7 @@ config CPU_BCLK_MHZ
config CONSOLE_UART_BASE_ADDRESS
hex
default 0xddffc000
default 0xcdffc000
depends on INTEL_LPSS_UART_FOR_CONSOLE
# M and N divisor values for clock frequency configuration.
@ -396,4 +396,7 @@ config HAVE_PAM0_REGISTER
bool
default n
config DOMAIN_RESOURCE_32BIT_LIMIT
default PCR_BASE_ADDRESS
endif