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soc/intel/common/block/gspi: set cs polarity before using 

Move call to __gspi_cs_change() in gspi_ctrlr_setup() to after
initialization of cs polarity since it requires polarity to be
set to work properly.  Failure to do so confuses cr50.

BUG=b:70628116
BRANCH=chromeos-2016.05
TEST='emerge-meowth coreboot' and verify on scope that chip select
polarity is correct for the first transaction.

Change-Id: I20b4f584663477d751a07889bccc865efbf9c469
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/25013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Nick Vaccaro 2017-12-20 17:18:01 -08:00 committed by Patrick Georgi
parent 5d6ab45dbb
commit cb06fab1fc
1 changed files with 3 additions and 3 deletions
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6
src/soc/intel/common/block/gspi/gspi.c
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@ -414,9 +414,6 @@ static int gspi_ctrlr_setup(const struct spi_slave *dev)
/* Take controller out of reset, keeping DMA in reset. */ /* Take controller out of reset, keeping DMA in reset. */
gspi_write_mmio_reg(p, RESETS, CTRLR_ACTIVE | DMA_RESET); gspi_write_mmio_reg(p, RESETS, CTRLR_ACTIVE | DMA_RESET);
/* De-assert chip select. */
__gspi_cs_change(p, CS_DEASSERT);
/* /*
* CS control: * CS control:
* - Set SW mode. * - Set SW mode.
@ -430,6 +427,9 @@ static int gspi_ctrlr_setup(const struct spi_slave *dev)
cs_ctrl |= gspi_csctrl_state(pol, CS_DEASSERT); cs_ctrl |= gspi_csctrl_state(pol, CS_DEASSERT);
gspi_write_mmio_reg(p, SPI_CS_CONTROL, cs_ctrl); gspi_write_mmio_reg(p, SPI_CS_CONTROL, cs_ctrl);
/* De-assert chip select. */
__gspi_cs_change(p, CS_DEASSERT);
/* Disable SPI controller. */ /* Disable SPI controller. */
gspi_write_mmio_reg(p, SSCR0, SSCR0_SSE_DISABLE); gspi_write_mmio_reg(p, SSCR0, SSCR0_SSE_DISABLE);