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soc/intel/common: remove nvm headers and c file 

There's no sense in having the nvm abstraction in its own files. Put
that support directly into mrc_cache.c.

BUG=b:69614064

Change-Id: I0f1a801c6e1a8c35f70faf9e4318bdc45955047a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Aaron Durbin 2017-12-14 13:53:14 -07:00
parent c3339ce9e3
commit cb0c40d350
4 changed files with 43 additions and 94 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/soc/intel/common/Makefile.inc
View File

@ -20,7 +20,6 @@ postcar-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
ramstage-y += hda_verb.c
ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
ramstage-y += util.c
ramstage-$(CONFIG_MMA) += mma.c

44
src/soc/intel/common/mrc_cache.c
View File

@ -17,6 +17,7 @@
#include <string.h>
#include <boot_device.h>
#include <bootstate.h>
#include <bootmode.h>
#include <console/console.h>
#include <cbmem.h>
#include <elog.h>
@ -24,9 +25,9 @@
#include <ip_checksum.h>
#include <region_file.h>
#include <security/vboot/vboot_common.h>
#include <spi_flash.h>
#include "mrc_cache.h"
#include "nvm.h"
#define DEFAULT_MRC_CACHE "RW_MRC_CACHE"
#define VARIABLE_MRC_CACHE "RW_VAR_MRC_CACHE"
@ -441,6 +442,47 @@ static void update_mrc_cache_by_type(int type)
log_event_cache_update(cr->elog_slot, UPDATE_SUCCESS);
}
/* Read flash status register to determine if write protect is active */
static int nvm_is_write_protected(void)
{
u8 sr1;
u8 wp_gpio;
u8 wp_spi;
if (!IS_ENABLED(CONFIG_CHROMEOS))
return 0;
if (!IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH))
return 0;
/* Read Write Protect GPIO if available */
wp_gpio = get_write_protect_state();
/* Read Status Register 1 */
if (spi_flash_status(boot_device_spi_flash(), &sr1) < 0) {
printk(BIOS_ERR, "Failed to read SPI status register 1\n");
return -1;
}
wp_spi = !!(sr1 & 0x80);
printk(BIOS_DEBUG, "SPI flash protection: WPSW=%d SRP0=%d\n",
wp_gpio, wp_spi);
return wp_gpio && wp_spi;
}
/* Apply protection to a range of flash */
static int nvm_protect(const struct region *r)
{
if (!IS_ENABLED(CONFIG_MRC_SETTINGS_PROTECT))
return 0;
if (!IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH))
return 0;
return spi_flash_ctrlr_protect_region(boot_device_spi_flash(), r);
}
/* Protect mrc region with a Protected Range Register */
static int protect_mrc_cache(const char *name)
{

65
src/soc/intel/common/nvm.c
View File

@ -1,65 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <stddef.h>
#include <bootmode.h>
#include <console/console.h>
#include <string.h>
#include <spi-generic.h>
#include <spi_flash.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "nvm.h"
/* Read flash status register to determine if write protect is active */
int nvm_is_write_protected(void)
{
u8 sr1;
u8 wp_gpio;
u8 wp_spi;
if (!IS_ENABLED(CONFIG_CHROMEOS))
return 0;
if (!IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH))
return 0;
/* Read Write Protect GPIO if available */
wp_gpio = get_write_protect_state();
/* Read Status Register 1 */
if (spi_flash_status(boot_device_spi_flash(), &sr1) < 0) {
printk(BIOS_ERR, "Failed to read SPI status register 1\n");
return -1;
}
wp_spi = !!(sr1 & 0x80);
printk(BIOS_DEBUG, "SPI flash protection: WPSW=%d SRP0=%d\n",
wp_gpio, wp_spi);
return wp_gpio && wp_spi;
}
/* Apply protection to a range of flash */
int nvm_protect(const struct region *r)
{
if (!IS_ENABLED(CONFIG_MRC_SETTINGS_PROTECT))
return 0;
if (!IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH))
return 0;
return spi_flash_ctrlr_protect_region(boot_device_spi_flash(), r);
}

27
src/soc/intel/common/nvm.h
View File

@ -1,27 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _COMMON_NVM_H_
#define _COMMON_NVM_H_
#include <commonlib/region.h>
/* Determine if flash device is write protected */
int nvm_is_write_protected(void);
/* Apply protection to a range of flash */
int nvm_protect(const struct region *region);
#endif /* _COMMON_NVM_H_ */