broadwell: Remove unused bootblock code
This code that stores the initial timestamp is not being used, instead the timestamp is passed to romstage_main(). BUG=chrome-os-partner:28234 BRANCH=samus,auron TEST=build and boot on samus Original-Change-Id: I0e0fa1ba74ab93d4454fdfa12208e712d2ae913c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/234402 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> (cherry picked from commit 838112cf79e2b4d51e5dc87d5ac9cd7e03807f29) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8fd7ba72c14c1e39f7bfa3a1ae8d03289a2abf73 Reviewed-on: http://review.coreboot.org/9698 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -18,24 +18,12 @@
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*/
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*/
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#include <arch/io.h>
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#include <arch/io.h>
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#include <cpu/x86/tsc.h>
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#include <soc/iomap.h>
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#include <soc/iomap.h>
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#include <soc/lpc.h>
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#include <soc/lpc.h>
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#include <soc/pci_devs.h>
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#include <soc/pci_devs.h>
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#include <soc/rcba.h>
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#include <soc/rcba.h>
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#include <soc/spi.h>
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#include <soc/spi.h>
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static void store_initial_timestamp(void)
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{
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/* Two 32bit scratchpad registers available:
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* D0:F0 0xdc (SKPAD)
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* D31:F2 0xd0 (SATA SP)
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*/
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tsc_t tsc = rdtsc();
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pci_write_config32(SA_DEV_ROOT, 0xdc, tsc.lo);
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pci_write_config32(PCH_DEV_SATA, 0xd0, tsc.hi);
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}
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/*
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/*
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* Enable Prefetching and Caching.
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* Enable Prefetching and Caching.
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*/
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*/
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@ -84,9 +72,6 @@ static void set_spi_speed(void)
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static void bootblock_southbridge_init(void)
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static void bootblock_southbridge_init(void)
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{
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{
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#if CONFIG_COLLECT_TIMESTAMPS
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store_initial_timestamp();
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#endif
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map_rcba();
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map_rcba();
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enable_spi_prefetch();
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enable_spi_prefetch();
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enable_port80_on_lpc();
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enable_port80_on_lpc();
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