google/nautilus: Update GPIO table
Update GPIO settings to meet nautilus's schematic design. BRANCH=master BUG=b:66462881 TEST=emerge-nautilus coreboot Change-Id: I11930df62130431764702371a3ba84949a65ba30 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: shkim <sh_.kim@samsung.com>
This commit is contained in:
Chris Wang
Furquan Shaikh
parent
cf24da4c53
commit
cb25974f5a
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@ -20,23 +20,23 @@
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/* Pad configuration in ramstage */
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/* Leave eSPI pins untouched from default settings */
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static const struct pad_config gpio_table[] = {
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/* A0 : RCIN# ==> NC(TP41) */
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/* A0 : RCIN# ==> NC(TP763) */
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PAD_CFG_NC(GPP_A0),
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/* A1 : ESPI_IO0 */
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/* A2 : ESPI_IO1 */
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/* A3 : ESPI_IO2 */
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/* A4 : ESPI_IO3 */
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/* A5 : ESPI_CS# */
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/* A6 : SERIRQ ==> NC(TP44) */
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/* A6 : SERIRQ ==> NC(TP764) */
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PAD_CFG_NC(GPP_A6),
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/* A7 : PIRQA# ==> NC(TP29) */
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/* A7 : PIRQA# ==> NC(TP703) */
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PAD_CFG_NC(GPP_A7),
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/* A8 : CLKRUN# ==> NC(TP45) */
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/* A8 : CLKRUN# ==> NC(TP758)) */
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PAD_CFG_NC(GPP_A8),
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/* A9 : ESPI_CLK */
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/* A10 : CLKOUT_LPC1 ==> NC */
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PAD_CFG_NC(GPP_A10),
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/* A11 : PME# ==> NC(TP67) */
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/* A11 : PME# ==> NC(TP726) */
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PAD_CFG_NC(GPP_A11),
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/* A12 : BM_BUSY# ==> NC */
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PAD_CFG_NC(GPP_A12),
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@ -45,61 +45,53 @@ static const struct pad_config gpio_table[] = {
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/* A14 : ESPI_RESET# */
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/* A15 : SUSACK# ==> SUSACK_L */
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PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
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/* A16 : SD_1P8_SEL ==> SD_PWR_1800_SEL */
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/* A16 : SD_1P8_SEL ==> CPU1_P1.8V_SEL */
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PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
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/* A17 : SD_PWR_EN# ==> EN_SD_SOCKET_PWR_L */
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/* A17 : SD_PWR_EN# ==> CPU1_SDCARD_PWREN_L */
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PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
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/* A18 : ISH_GP0 ==> NC */
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PAD_CFG_NC(GPP_A18),
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/* A19 : ISH_GP1 ==> NC */
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PAD_CFG_NC(GPP_A19),
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/* A20 : ISH_GP2 ==> ACCEL_GYRO_INT_L */
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PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST),
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/* A21 : ISH_GP3 ==> NC */
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PAD_CFG_NC(GPP_A21),
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/* A22 : ISH_GP4 ==> NC */
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PAD_CFG_NC(GPP_A22),
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/* A23 : ISH_GP5 ==> NC */
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PAD_CFG_NC(GPP_A23),
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/* A20 : ISH_GP2 ==> NC */
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PAD_CFG_NC(GPP_A20),
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/* A21 : ISH_GP3 ==> CHP1_DIG_PDCT_L */
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PAD_CFG_GPI_APIC(GPP_A21, NONE, PLTRST),
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/* A22 : ISH_GP4 ==> CHP1_DIG_IRQ_L */
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PAD_CFG_GPI_APIC(GPP_A22, NONE, PLTRST),
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/* A23 : ISH_GP5 ==> CHP1_SPK_PA_EN */
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PAD_CFG_GPO(GPP_A23, 1, DEEP),
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/* B0 : CORE_VID0 ==> NC(TP42) */
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/* B0 : CORE_VID0 ==> NC(TP721) */
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PAD_CFG_NC(GPP_B0),
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/* B1 : CORE_VID1 ==> NC(TP43) */
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/* B1 : CORE_VID1 ==> NC(TP722) */
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PAD_CFG_NC(GPP_B1),
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/* B2 : VRALERT# ==> NC */
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PAD_CFG_NC(GPP_B2),
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/* B3 : CPU_GP2 ==> NC */
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PAD_CFG_NC(GPP_B3),
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/* B3 : CPU_GP2 ==> CHP3_TP_INT_L */
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PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST),
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/* B4 : CPU_GP3 ==> NC */
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PAD_CFG_NC(GPP_B4),
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/* B5 : SRCCLKREQ0# ==> NC */
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PAD_CFG_NC(GPP_B5),
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/* B6 : SRCCLKREQ1# ==> WLAN_PCIE_CLKREQ_L */
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/* B5 : SRCCLKREQ0# ==> CHP3_TP_INT_L - for wake event */
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PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, INVERT),
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/* B6 : SRCCLKREQ1# ==> CHP3_WLAN_CLKREQ_L */
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PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
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/* B7 : SRCCLKREQ2# ==> NC */
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PAD_CFG_NC(GPP_B7),
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/* B8 : SRCCLKREQ3# ==> CHP3_WLAN_PE_RST */
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PAD_CFG_GPO(GPP_B8, 0, DEEP),
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/* B9 : SRCCLKREQ4# ==> NC */
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PAD_CFG_NC(GPP_B9),
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/* B10 : SRCCLKREQ5# ==> NC */
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PAD_CFG_NC(GPP_B10),
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/* B11 : EXT_PWR_GATE# ==> NC */
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PAD_CFG_NC(GPP_B11),
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/* B12 : SLP_S0# ==> SLP_S0_L_G */
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/* B12 : SLP_S0# ==> CHP3_SLPS0_L_ORG */
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PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
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/* B13 : PLTRST# ==> PLT_RST_L */
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/* B13 : PLTRST# ==> PLT3_RST_L */
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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/* B14 : SPKR ==> NC */
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PAD_CFG_NC(GPP_B14),
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#if IS_ENABLED(CONFIG_POPPY_USE_SPI_TPM)
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/* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */
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PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
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/* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */
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PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
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/* B17 : GSPI0_MISO ==> PCH_SPI_H1_3V3_MISO */
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
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/* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */
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PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
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#else
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/* B15 : GSPI0_CS# ==> NC */
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PAD_CFG_NC(GPP_B15),
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/* B16 : GSPI0_CLK ==> NC */
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@ -108,22 +100,21 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NC(GPP_B17),
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/* B18 : GSPI0_MOSI ==> NC */
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PAD_CFG_NC(GPP_B18),
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#endif
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/* B19 : GSPI1_CS# ==> NC */
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PAD_CFG_NC(GPP_B19),
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/* B19 : GSPI1_CS# ==> CHP3_PEN_EJECT - for notification */
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PAD_CFG_GPI(GPP_B19, NONE, DEEP),
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/* B20 : GSPI1_CLK ==> NC */
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PAD_CFG_NC(GPP_B20),
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/* B21 : GSPI1_MISO ==> NC */
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PAD_CFG_NC(GPP_B21),
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/* B21 : GSPI1_MISO ==> CHP3_PEN_EJECT - for wake event */
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PAD_CFG_GPI_ACPI_SCI(GPP_B21, NONE, DEEP, NONE),
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/* B22 : GSPI1_MOSI ==> NC */
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PAD_CFG_NC(GPP_B22),
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/* B23 : SM1ALERT# ==> NC */
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PAD_CFG_NC(GPP_B23),
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/* C0 : SMBCLK ==> NC */
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PAD_CFG_NC(GPP_C0),
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/* C1 : SMBDATA ==> NC */
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PAD_CFG_NC(GPP_C1),
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/* C0 : SMBCLK ==> CHP3_SMBCLK */
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PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
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/* C1 : SMBDATA ==> CHP3_SMBDATA */
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PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
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/* C2 : SMBALERT# ==> NC */
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PAD_CFG_NC(GPP_C2),
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/* C3 : SML0CLK ==> NC */
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@ -132,17 +123,17 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NC(GPP_C4),
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/* C5 : SML0ALERT# ==> NC */
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PAD_CFG_NC(GPP_C5),
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/* C6 : SM1CLK ==> EC_IN_RW_OD */
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/* C6 : SM1CLK ==> CPU3_EC_IN_RW */
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PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP),
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/* C7 : SM1DATA ==> NC */
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PAD_CFG_NC(GPP_C7),
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/* C8 : UART0_RXD ==> FP_INT */
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PAD_CFG_GPI_APIC(GPP_C8, NONE, PLTRST),
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/* C9 : UART0_TXD ==> FP_RST_ODL */
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PAD_CFG_GPO(GPP_C9, 0, DEEP),
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/* C10 : UART0_RTS# ==> EC_CAM_PMIC_RST_L */
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/* C8 : UART0_RXD ==> NC */
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PAD_CFG_NC(GPP_C8),
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/* C9 : UART0_TXD ==> CHP3_P3.3V_DX_DIG_EN */
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PAD_CFG_GPO(GPP_C9, 1, DEEP),
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/* C10 : UART0_RTS# ==> CHP3_CAM_PMIC_RST_L */
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PAD_CFG_GPO(GPP_C10, 1, DEEP),
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/* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM */
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/* C11 : UART0_CTS# ==> CHP3_P3.3V_DX_CAM_EN */
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PAD_CFG_GPO(GPP_C11, 1, DEEP),
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/* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */
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PAD_CFG_GPI(GPP_C12, NONE, DEEP),
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@ -152,28 +143,21 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_GPI(GPP_C14, NONE, DEEP),
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/* C15 : UART1_CTS# ==> PCH_MEM_CONFIG[3] */
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PAD_CFG_GPI(GPP_C15, NONE, DEEP),
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/* C16 : I2C0_SDA ==> PCH_I2C0_TOUCHSCREEN_3V3_SDA */
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/* C16 : I2C0_SDA ==> CHP3_I2C0_TSP_SDA */
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PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
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/* C17 : I2C0_SCL ==> PCH_I2C0_TOUCHSCREEN_3V3_SCL */
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/* C17 : I2C0_SCL ==> CHP3_I2C0_TSP_SCL */
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PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
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#if IS_ENABLED(CONFIG_POPPY_USE_I2C_TPM)
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/* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */
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PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
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/* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */
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PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
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#else
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/* C18 : I2C1_SDA ==> NC */
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PAD_CFG_NC(GPP_C18),
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/* C19 : I2C1_SCL ==> NC */
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PAD_CFG_NC(GPP_C19),
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#endif
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/* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */
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/* C20 : UART2_RXD ==> CHP3_RX_SERVO_TX_UART */
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PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
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/* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */
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/* C21 : UART2_TXD ==> CHP3_TX_SERVO_RX_UART */
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PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
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/* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */
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/* C22 : UART2_RTS# ==> CHP3_P3.3V_DX_TSP_EN */
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PAD_CFG_GPO(GPP_C22, 0, DEEP),
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/* C23 : UART2_CTS# ==> PCH_WP */
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/* C23 : UART2_CTS# ==> CHP3_PCH_WP*/
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PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),
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/* D0 : SPI1_CS# ==> NC */
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@ -184,22 +168,22 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NC(GPP_D2),
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/* D3 : SPI1_MOSI ==> NC */
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PAD_CFG_NC(GPP_D3),
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/* D4 : FASHTRIG ==> NC */
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/* D4 : FASHTRIG ==> CHP1_VDD_CAM_CORE_EN */
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PAD_CFG_NC(GPP_D4),
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/* D5 : ISH_I2C0_SDA ==> ISH_I2C_SENSOR_1V8_SDA */
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/* D5 : ISH_I2C0_SDA ==> CHP1_I2C_ISH_SENSOR_SDA */
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PAD_CFG_NF_1V8(GPP_D5, NONE, DEEP, NF1),
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/* D6 : ISH_I2C0_SCL ==> ISH_I2C_SENSOR_1V8_SCL */
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/* D6 : ISH_I2C0_SCL ==> CHP1_I2C_ISH_SENSOR_SCL */
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PAD_CFG_NF_1V8(GPP_D6, NONE, DEEP, NF1),
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/* D7 : ISH_I2C1_SDA ==> NC */
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PAD_CFG_NC(GPP_D7),
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/* D8 : ISH_I2C1_SCL ==> NC */
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PAD_CFG_NC(GPP_D8),
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/* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */
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PAD_CFG_GPI(GPP_D9, NONE, PLTRST),
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/* D10 : ISH_SPI_CLK ==> SPKR_RST_L */
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PAD_CFG_GPO(GPP_D10, 1, DEEP),
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/* D11 : ISH_SPI_MISO ==> SPKR_INT_L */
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PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST),
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/* D9 : ISH_SPI_CS# ==> CHP1_HEADSET_INT_L */
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PAD_CFG_GPI_APIC_INVERT(GPP_D9, NONE, DEEP),
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/* D10 : ISH_SPI_CLK ==> NC */
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PAD_CFG_NC(GPP_D10),
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/* D11 : ISH_SPI_MISO ==> NC */
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PAD_CFG_NC(GPP_D11),
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/* D12 : ISH_SPI_MOSI ==> NC */
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PAD_CFG_NC(GPP_D12),
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/* D13 : ISH_UART0_RXD ==> NC */
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@ -220,44 +204,44 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
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/* D21 : SPI1_IO2 ==> NC */
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PAD_CFG_NC(GPP_D21),
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/* D22 : SPI1_IO3 ==> BOOT_BEEP_OVERRIDE */
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/* D22 : SPI1_IO3 ==> CHP1_BOOT_BEEP_OVERRIDE */
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PAD_CFG_GPO(GPP_D22, 1, DEEP),
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/* D23 : I2S_MCLK ==> I2S_MCLK_R */
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/* D23 : I2S_MCLK ==> CHP1_I2S_MCLK */
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PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
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/* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */
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/* E0 : SATAXPCI0 ==> CHP3_HAVEN_INT_L */
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PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),
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/* E1 : SATAXPCIE1 ==> NC */
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PAD_CFG_NC(GPP_E1),
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/* E2 : SATAXPCIE2 ==> NC */
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PAD_CFG_NC(GPP_E2),
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/* E3 : CPU_GP0 ==> TOUCHSCREEN_RST_L */
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PAD_CFG_GPO(GPP_E3, 0, DEEP),
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/* E3 : CPU_GP0 ==> NC */
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PAD_CFG_NC(GPP_E3),
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/* E4 : SATA_DEVSLP0 ==> NC */
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PAD_CFG_NC(GPP_E4),
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/* E5 : SATA_DEVSLP1 ==> NC */
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PAD_CFG_NC(GPP_E5),
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/* E6 : SATA_DEVSLP2 ==> NC */
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PAD_CFG_NC(GPP_E6),
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/* E7 : CPU_GP1 ==> TOUCHSCREEN_INT_L */
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/* E7 : CPU_GP1 ==> CHP3_TSP_INT_L */
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PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST),
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/* E8 : SATALED# ==> NC */
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PAD_CFG_NC(GPP_E8),
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/* E9 : USB2_OCO# ==> USB_C0_OC_ODL */
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/* E9 : USB2_OCO# ==> USB3_C1_OC1_L */
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PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
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/* E10 : USB2_OC1# ==> USB_C1_OC_ODL */
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/* E10 : USB2_OC1# ==> USB3_C0_OC0_L */
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PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
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/* E11 : USB2_OC2# ==> TOUCHSCREEN_STOP_L */
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PAD_CFG_GPO(GPP_E11, 0, DEEP),
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/* E11 : USB2_OC2# ==> NC */
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PAD_CFG_NC(GPP_E11),
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/* E12 : USB2_OC3# ==> USB2_OC3_L */
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PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
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/* E13 : DDPB_HPD0 ==> USB_C0_DP_HPD */
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/* E13 : DDPB_HPD0 ==> KBC3_USB_C0_DP_HPD */
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PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1),
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/* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */
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/* E14 : DDPC_HPD1 ==> KBC3_USB_C1_DP_HPD */
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PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1),
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/* E15 : DDPD_HPD2 ==> SD_CD# */
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/* E15 : DDPD_HPD2 ==> CPU3_SD_CD_L */
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PAD_CFG_GPI(GPP_E15, 20K_PU, DEEP),
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/* E16 : DDPE_HPD3 ==> NC(TP244) */
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/* E16 : DDPE_HPD3 ==> NC(TP766) */
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PAD_CFG_NC(GPP_E16),
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/* E17 : EDP_HPD */
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PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
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@ -275,29 +259,29 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NC(GPP_E23),
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/* The next 4 pads are for bit banging the amplifiers, default to I2S */
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/* F0 : I2S2_SCLK ==> I2S2_SCLK_SPKR_R */
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/* F0 : I2S2_SCLK ==> CHP1_I2S2_SCLK_SPKR_R */
|
||||
PAD_CFG_GPI(GPP_F0, NONE, DEEP),
|
||||
/* F1 : I2S2_SFRM ==> I2S2_SFRM_SPKR_R */
|
||||
/* F1 : I2S2_SFRM ==> CHP1_I2S2_SFRM_SPKR_R*/
|
||||
PAD_CFG_GPI(GPP_F1, NONE, DEEP),
|
||||
/* F2 : I2S2_TXD ==> I2S2_PCH_TX_SPKR_RX_R */
|
||||
/* F2 : I2S2_TXD ==> CHP1_I2S2_PCH_TX_SPKR_RX_R */
|
||||
PAD_CFG_GPI(GPP_F2, NONE, DEEP),
|
||||
/* F3 : I2S2_RXD */
|
||||
PAD_CFG_GPI(GPP_F3, NONE, DEEP),
|
||||
/* F4 : I2C2_SDA ==> PCH_I2C2_CAM_PMIC_1V8_SDA */
|
||||
/* F4 : I2C2_SDA ==> CHP1_I2C2_CAM_PMIC_SDA */
|
||||
PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1),
|
||||
/* F5 : I2C2_SCL ==> PCH_I2C2_CAM_PMIC_1V8_SCL */
|
||||
/* F5 : I2C2_SCL ==> CHP1_I2C2_CAM_PMIC_SCL */
|
||||
PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1),
|
||||
/* F6 : I2C3_SDA ==> PCH_I2C3_PEN_1V8_SDA */
|
||||
PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1),
|
||||
/* F7 : I2C3_SCL ==> PCH_I2C3_PEN_1V8_SCL */
|
||||
PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1),
|
||||
/* F8 : I2C4_SDA ==> PCH_I2C4_UFCAM_1V8_SDA */
|
||||
/* F6 : I2C3_SDA ==> CHP1_I2C3_DIG_SDA */
|
||||
PAD_CFG_NF_1V8(GPP_F6, 5K_PU, DEEP, NF1),
|
||||
/* F7 : I2C3_SCL ==> CHP1_I2C3_DIG_SCL */
|
||||
PAD_CFG_NF_1V8(GPP_F7, 5K_PU, DEEP, NF1),
|
||||
/* F8 : I2C4_SDA ==> CHP1_I2C4_TP_SDA */
|
||||
PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),
|
||||
/* F9 : I2C4_SCL ==> PCH_I2C4_UFCAM_1V8_SCL */
|
||||
/* F9 : I2C4_SCL ==> CHP1_I2C4_TP_SCL */
|
||||
PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),
|
||||
/* F10 : I2C5_SDA ==> PCH_I2C5_AUDIO_1V8_SDA */
|
||||
/* F10 : I2C5_SDA ==> CHP1_I2C5_AUDIO_SDA */
|
||||
PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF1),
|
||||
/* F11 : I2C5_SCL ==> PCH_I2C5_AUDIO_1V8_SCL */
|
||||
/* F11 : I2C5_SCL ==> CHP1_I2C5_AUDIO_SCL */
|
||||
PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF1),
|
||||
/* F12 : EMMC_CMD */
|
||||
PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
|
||||
|
|
@ -341,27 +325,27 @@ static const struct pad_config gpio_table[] = {
|
|||
/* G7 : SD_WP */
|
||||
PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1),
|
||||
|
||||
/* GPD0: BATLOW# ==> PCH_BATLOW_L */
|
||||
/* GPD0: BATLOW# ==> CHP3_BATLOW# */
|
||||
PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
|
||||
/* GPD1: ACPRESENT ==> EC_PCH_ACPRESENT */
|
||||
/* GPD1: ACPRESENT ==> KBC3_AC_PRESENT */
|
||||
PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
|
||||
/* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R_L */
|
||||
/* GPD2: LAN_WAKE# ==> KBC3_PCH_WAKE_L */
|
||||
PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
|
||||
/* GPD3: PWRBTN# ==> PCH_PWR_BTN_L */
|
||||
/* GPD3: PWRBTN# ==> KBC3_PWRBTN_L */
|
||||
PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1),
|
||||
/* GPD4: SLP_S3# ==> SLP_S3_L */
|
||||
/* GPD4: SLP_S3# ==> CHP3_SLPS3_L */
|
||||
PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
||||
/* GPD5: SLP_S4# ==> SLP_S4_L */
|
||||
/* GPD5: SLP_S4# ==> CHP3_SLPS4_L */
|
||||
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
||||
/* GPD6: SLP_A# ==> NC(TP26) */
|
||||
/* GPD6: SLP_A# ==> NC(TP725) */
|
||||
PAD_CFG_NC(GPD6),
|
||||
/* GPD7: RSVD ==> NC */
|
||||
PAD_CFG_NC(GPD7),
|
||||
/* GPD8: SUSCLK ==> PCH_SUSCLK */
|
||||
/* GPD8: SUSCLK ==> CHP3_SUSCLK */
|
||||
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||
/* GPD9: SLP_WLAN# ==> NC(TP25) */
|
||||
/* GPD9: SLP_WLAN# ==> NC(TP724) */
|
||||
PAD_CFG_NC(GPD9),
|
||||
/* GPD10: SLP_S5# ==> NC(TP15) */
|
||||
/* GPD10: SLP_S5# ==> NC(TP742) */
|
||||
PAD_CFG_NC(GPD10),
|
||||
/* GPD11: LANPHYC ==> NC */
|
||||
PAD_CFG_NC(GPD11),
|
||||
|
|
@ -369,26 +353,10 @@ static const struct pad_config gpio_table[] = {
|
|||
|
||||
/* Early pad configuration in bootblock */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
/* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */
|
||||
PAD_CFG_GPO(GPP_B8, 0, DEEP),
|
||||
|
||||
#if IS_ENABLED(CONFIG_POPPY_USE_SPI_TPM)
|
||||
/* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */
|
||||
PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
|
||||
/* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */
|
||||
PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
|
||||
/* B17 : GSPI0_MISO ==> PCH_SPI_H1_3V3_MISO */
|
||||
PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
|
||||
/* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */
|
||||
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_POPPY_USE_I2C_TPM)
|
||||
/* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */
|
||||
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
|
||||
/* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */
|
||||
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
|
||||
#endif
|
||||
|
||||
/* Ensure UART pins are in native mode for H1. */
|
||||
/* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */
|
||||
|
|
|
|||
Loading…
Reference in New Issue