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This patch reverts SuperIO changes that I was too hasty with. Even though the 

address of the RTC is 0x70, you need to write 0x400 to it.  Now the dump from
superiotool matches the factory except 0xf0 of the keyboard.  When you boot with
the factory BIOS that is 0x04, but with coreboot it is not set.

It's trivial because it is reverts.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4002 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson 2009-03-13 17:20:59 +00:00
parent 65e9bc13f0
commit cb2de6869c
3 changed files with 5 additions and 6 deletions
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7
src/mainboard/tyan/s2895/Config.lb
View File

@ -269,7 +269,7 @@ chip northbridge/amd/amdk8/root_complex
device pnp 2e.3 on # Parallel Port device pnp 2e.3 on # Parallel Port
io 0x60 = 0x378 io 0x60 = 0x378
irq 0x70 = 7 irq 0x70 = 7
drq 0x74 = 3 drq 0x74 = 4
end end
device pnp 2e.4 on # Com1 device pnp 2e.4 on # Com1
io 0x60 = 0x3f8 io 0x60 = 0x3f8
@ -286,7 +286,7 @@ chip northbridge/amd/amdk8/root_complex
irq 0x72 = 12 irq 0x72 = 12
end end
device pnp 2e.8 on # HW Monitor device pnp 2e.8 on # HW Monitor
io 0x60 = 0x290 io 0x60 = 0x480
chip drivers/generic/generic # LM95221 CPU temp chip drivers/generic/generic # LM95221 CPU temp
device i2c 2b on end device i2c 2b on end
end end
@ -295,8 +295,7 @@ chip northbridge/amd/amdk8/root_complex
end end
end end
device pnp 2e.a on # RT device pnp 2e.a on # RT
io 0x60 = 0x90 io 0x60 = 0x400
irq 0x70 = 8
end end
end end
end end

2
src/mainboard/tyan/s2895/dsdt.dsl
View File

@ -188,7 +188,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1)
Method (_CRS, 0, NotSerialized) Method (_CRS, 0, NotSerialized)
{ {
Name (TMP, ResourceTemplate () { Name (TMP, ResourceTemplate () {
FixedIO (0x0090, 0x02) FixedIO (0x0070, 0x02)
IRQNoFlags () {8} IRQNoFlags () {8}
}) })
Return (TMP) Return (TMP)

2
src/superio/smsc/lpc47b397/superio.c
View File

@ -202,7 +202,7 @@ static struct pnp_info pnp_dev_info[] = {
{ &ops, LPC47B397_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, { &ops, LPC47B397_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, LPC47B397_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, { &ops, LPC47B397_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
{ &ops_hwm, LPC47B397_HWM, PNP_IO0, { 0x7f0, 0 }, }, { &ops_hwm, LPC47B397_HWM, PNP_IO0, { 0x7f0, 0 }, },
{ &ops, LPC47B397_RT, PNP_IO0 | PNP_IRQ0, { 0x7fc, 0 }, }, { &ops, LPC47B397_RT, PNP_IO0, { 0x780, 0 }, },
}; };
static void enable_dev(struct device *dev) static void enable_dev(struct device *dev)