From cb2fd20c7f5cf43776dddfe2dbafeb19475e81f3 Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Wed, 9 Jun 2021 19:27:06 +0530 Subject: [PATCH] soc/intel/common: Add HECI Reset flow in the CSE driver This change is required as part of HECI Interface initialization in order to put the host and CSE into a known good state for communication. Please refer ME BIOS specification for more details. The change adds HECI interface reset flow in the CSE driver. It enables coreboot to send HECI commands before DRAM Init. BUG=b:175516533 TEST=Run 50 cold reset cycles on Brya Signed-off-by: Sridhar Siricilla Change-Id: Ie078beaa33c6a35ae8f5f460d4354766aa710fba Reviewed-on: https://review.coreboot.org/c/coreboot/+/55363 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/common/block/cse/cse.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index e41e337550..68a41e869c 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -111,6 +111,9 @@ void heci_init(uintptr_t tempbar) /* Enable Bus Master and MMIO Space */ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + + /* Trigger HECI Reset and make Host ready for communication with CSE */ + heci_reset(); } static uint32_t read_bar(pci_devfn_t dev, uint32_t offset)