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google/trogdor: Add backlight support for Parade ps8640 

Add backlight support in ps8640 through the AUX channel using eDP
DPCD registers.

BUG=b:202966352
BRANCH=trogdor
TEST=verified firmware screen works on homestar rev4

Change-Id: Ief1bf56c89c8215427dcbddfc67e8bcd4c3607d2
Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
xuxinxiong 2021-10-26 20:16:21 +08:00 committed by Patrick Georgi
parent 73161c644e
commit cb3745c407
6 changed files with 219 additions and 77 deletions
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100
src/drivers/parade/ps8640/ps8640.c
View File

@ -5,7 +5,7 @@
#include <edid.h>
#include <console/console.h>
#include <timer.h>
#include <dp_aux.h>
#include "ps8640.h"
int ps8640_get_edid(uint8_t bus, uint8_t chip, struct edid *out)
@ -80,3 +80,101 @@ int ps8640_init(uint8_t bus, uint8_t chip)
return 0;
}
static cb_err_t ps8640_bridge_aux_request(uint8_t bus,
uint8_t chip,
unsigned int target_reg,
unsigned int total_size,
enum aux_request request,
uint8_t *data)
{
int i;
uint32_t length;
uint8_t buf;
uint8_t reg;
int ret;
if (target_reg & ~SWAUX_ADDR_MASK)
return CB_ERR;
while (total_size) {
length = MIN(total_size, DP_AUX_MAX_PAYLOAD_BYTES);
total_size -= length;
ret = i2c_writeb(bus, chip, PAGE0_AUXCH_CFG3, AUXCH_CFG3_RESET);
if (ret)
return CB_ERR;
enum i2c_over_aux cmd = dp_get_aux_cmd(request, total_size);
if (i2c_writeb(bus, chip, PAGE0_SWAUX_ADDR_23_16,
(target_reg >> 16) | (cmd << 4)) ||
i2c_writeb(bus, chip, PAGE0_SWAUX_ADDR_15_8, target_reg >> 8) ||
i2c_writeb(bus, chip, PAGE0_SWAUX_ADDR_7_0, target_reg)) {
return CB_ERR;
}
if (dp_aux_request_is_write(request)) {
reg = PAGE0_SWAUX_WDATA;
for (i = 0; i < length; i++) {
ret = i2c_writeb(bus, chip, reg++, *data++);
if (ret)
return CB_ERR;
}
} else {
if (length == 0)
i2c_writeb(bus, chip, PAGE0_SWAUX_LENGTH, SWAUX_NO_PAYLOAD);
else
i2c_writeb(bus, chip, PAGE0_SWAUX_LENGTH, length - 1);
}
ret = i2c_writeb(bus, chip, PAGE0_SWAUX_CTRL, SWAUX_SEND);
if (ret)
return CB_ERR;
if (!wait_ms(100, !i2c_readb(bus, chip, PAGE0_SWAUX_CTRL, &buf) &&
!(buf & SWAUX_SEND)))
return CB_ERR;
if (i2c_readb(bus, chip, PAGE0_SWAUX_STATUS, &buf))
return CB_ERR;
switch (buf & SWAUX_STATUS_MASK) {
case SWAUX_STATUS_NACK:
case SWAUX_STATUS_I2C_NACK:
case SWAUX_STATUS_INVALID:
case SWAUX_STATUS_TIMEOUT:
return CB_ERR;
case SWAUX_STATUS_ACKM:
length = buf & SWAUX_M_MASK;
break;
}
if (length && !dp_aux_request_is_write(request)) {
reg = PAGE0_SWAUX_RDATA;
for (i = 0; i < length; i++) {
if (i2c_readb(bus, chip, reg++, &buf))
return CB_ERR;
*data++ = buf;
}
}
}
return CB_SUCCESS;
}
void ps8640_backlight_enable(uint8_t bus, uint8_t chip)
{
uint8_t val;
val = DP_BACKLIGHT_CONTROL_MODE_DPCD;
ps8640_bridge_aux_request(bus, chip, DP_BACKLIGHT_MODE_SET, 1,
DPCD_WRITE, &val);
val = 0xff;
ps8640_bridge_aux_request(bus, chip, DP_BACKLIGHT_BRIGHTNESS_MSB, 1,
DPCD_WRITE, &val);
val = DP_BACKLIGHT_ENABLE;
ps8640_bridge_aux_request(bus, chip, DP_DISPLAY_CONTROL_REGISTER, 1,
DPCD_WRITE, &val);
}

28
src/drivers/parade/ps8640/ps8640.h
View File

@ -24,11 +24,33 @@ enum {
};
enum {
EDID_LENGTH = 128,
EDID_I2C_ADDR = 0x50,
EDID_EXTENSION_FLAG = 0x7e,
PAGE0_AUXCH_CFG3 = 0x76,
AUXCH_CFG3_RESET = 0xff,
PAGE0_SWAUX_ADDR_7_0 = 0x7d,
PAGE0_SWAUX_ADDR_15_8 = 0x7e,
PAGE0_SWAUX_ADDR_23_16 = 0x7f,
SWAUX_ADDR_MASK = 0xfffff,
PAGE0_SWAUX_LENGTH = 0x80,
SWAUX_LENGTH_MASK = 0xf,
SWAUX_NO_PAYLOAD = BIT(7),
PAGE0_SWAUX_WDATA = 0x81,
PAGE0_SWAUX_RDATA = 0x82,
PAGE0_SWAUX_CTRL = 0x83,
SWAUX_SEND = BIT(0),
PAGE0_SWAUX_STATUS = 0x84,
SWAUX_M_MASK = 0x1f,
SWAUX_STATUS_MASK = (0x7 << 5),
SWAUX_STATUS_NACK = (0x1 << 5),
SWAUX_STATUS_DEFER = (0x2 << 5),
SWAUX_STATUS_ACKM = (0x3 << 5),
SWAUX_STATUS_INVALID = (0x4 << 5),
SWAUX_STATUS_I2C_NACK = (0x5 << 5),
SWAUX_STATUS_I2C_DEFER = (0x6 << 5),
SWAUX_STATUS_TIMEOUT = (0x7 << 5),
};
int ps8640_init(uint8_t bus, uint8_t chip);
int ps8640_get_edid(uint8_t bus, uint8_t chip, struct edid *out);
void ps8640_backlight_enable(uint8_t bus, uint8_t chip);
#endif

78
src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c
View File

@ -4,6 +4,7 @@
#include <delay.h>
#include <endian.h>
#include <device/i2c_simple.h>
#include <dp_aux.h>
#include <edid.h>
#include <timer.h>
#include <types.h>
@ -31,14 +32,6 @@
#define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
#define DP_LANE_COUNT_MASK 0xf
/* Backlight configuration */
#define DP_BACKLIGHT_MODE_SET 0x721
#define DP_BACKLIGHT_CONTROL_MODE_MASK 0x3
#define DP_BACKLIGHT_CONTROL_MODE_DPCD 0x2
#define DP_DISPLAY_CONTROL_REGISTER 0x720
#define DP_BACKLIGHT_ENABLE 0x1
#define DP_BACKLIGHT_BRIGHTNESS_MSB 0x722
/* link configuration */
#define DP_LINK_BW_SET 0x100
#define DP_LINK_BW_1_62 0x06
@ -132,17 +125,6 @@ enum vstream_config {
VSTREAM_ENABLE = 1,
};
enum i2c_over_aux {
I2C_OVER_AUX_WRITE_MOT_0 = 0x0,
I2C_OVER_AUX_READ_MOT_0 = 0x1,
I2C_OVER_AUX_WRITE_STATUS_UPDATE_0 = 0x2,
I2C_OVER_AUX_WRITE_MOT_1 = 0x4,
I2C_OVER_AUX_READ_MOT_1 = 0x5,
I2C_OVER_AUX_WRITE_STATUS_UPDATE_1 = 0x6,
NATIVE_AUX_WRITE = 0x8,
NATIVE_AUX_READ = 0x9,
};
enum aux_cmd_status {
NAT_I2C_FAIL = 1 << 6,
AUX_SHORT = 1 << 5,
@ -166,21 +148,6 @@ enum ml_tx_mode {
REDRIVER_SEMI_AUTO_LINK_TRAINING = 0xb,
};
enum aux_request {
DPCD_READ,
DPCD_WRITE,
I2C_RAW_READ,
I2C_RAW_WRITE,
I2C_RAW_READ_AND_STOP,
I2C_RAW_WRITE_AND_STOP,
};
enum {
EDID_LENGTH = 128,
EDID_I2C_ADDR = 0x50,
EDID_EXTENSION_FLAG = 0x7e,
};
/*
* LUT index corresponds to register value and LUT values corresponds
* to dp data rate supported by the bridge in Mbps unit.
@ -189,41 +156,6 @@ static const unsigned int sn65dsi86_bridge_dp_rate_lut[] = {
0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
};
static bool request_is_write(enum aux_request request)
{
switch (request) {
case I2C_RAW_WRITE_AND_STOP:
case I2C_RAW_WRITE:
case DPCD_WRITE:
return true;
default:
return false;
}
}
static enum i2c_over_aux get_aux_cmd(enum aux_request request, uint32_t remaining_after_this)
{
switch (request) {
case I2C_RAW_WRITE_AND_STOP:
if (!remaining_after_this)
return I2C_OVER_AUX_WRITE_MOT_0;
/* fallthrough */
case I2C_RAW_WRITE:
return I2C_OVER_AUX_WRITE_MOT_1;
case I2C_RAW_READ_AND_STOP:
if (!remaining_after_this)
return I2C_OVER_AUX_READ_MOT_0;
/* fallthrough */
case I2C_RAW_READ:
return I2C_OVER_AUX_READ_MOT_1;
case DPCD_WRITE:
return NATIVE_AUX_WRITE;
case DPCD_READ:
default:
return NATIVE_AUX_READ;
}
}
static cb_err_t sn65dsi86_bridge_aux_request(uint8_t bus,
uint8_t chip,
unsigned int target_reg,
@ -241,10 +173,10 @@ static cb_err_t sn65dsi86_bridge_aux_request(uint8_t bus,
NAT_I2C_FAIL | AUX_SHORT | AUX_DFER | AUX_RPLY_TOUT | SEND_INT);
while (total_size) {
length = MIN(total_size, 16);
length = MIN(total_size, DP_AUX_MAX_PAYLOAD_BYTES);
total_size -= length;
enum i2c_over_aux cmd = get_aux_cmd(request, total_size);
enum i2c_over_aux cmd = dp_get_aux_cmd(request, total_size);
if (i2c_writeb(bus, chip, SN_AUX_CMD_REG, (cmd << 4)) ||
i2c_writeb(bus, chip, SN_AUX_ADDR_19_16_REG, (target_reg >> 16) & 0xF) ||
i2c_writeb(bus, chip, SN_AUX_ADDR_15_8_REG, (target_reg >> 8) & 0xFF) ||
@ -252,7 +184,7 @@ static cb_err_t sn65dsi86_bridge_aux_request(uint8_t bus,
i2c_writeb(bus, chip, SN_AUX_LENGTH_REG, length))
return CB_ERR;
if (request_is_write(request)) {
if (dp_aux_request_is_write(request)) {
reg = SN_AUX_WDATA_REG_0;
for (i = 0; i < length; i++)
if (i2c_writeb(bus, chip, reg++, *data++))
@ -273,7 +205,7 @@ static cb_err_t sn65dsi86_bridge_aux_request(uint8_t bus,
return CB_ERR;
}
if (!request_is_write(request)) {
if (!dp_aux_request_is_write(request)) {
reg = SN_AUX_RDATA_REG_0;
for (i = 0; i < length; i++) {
if (i2c_readb(bus, chip, reg++, &buf))

48
src/include/dp_aux.h Normal file
View File

@ -0,0 +1,48 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _DP_AUX_H_
#define _DP_AUX_H_
#include <types.h>
enum {
EDID_LENGTH = 128,
EDID_I2C_ADDR = 0x50,
EDID_EXTENSION_FLAG = 0x7e,
};
enum i2c_over_aux {
I2C_OVER_AUX_WRITE_MOT_0 = 0x0,
I2C_OVER_AUX_READ_MOT_0 = 0x1,
I2C_OVER_AUX_WRITE_STATUS_UPDATE_0 = 0x2,
I2C_OVER_AUX_WRITE_MOT_1 = 0x4,
I2C_OVER_AUX_READ_MOT_1 = 0x5,
I2C_OVER_AUX_WRITE_STATUS_UPDATE_1 = 0x6,
NATIVE_AUX_WRITE = 0x8,
NATIVE_AUX_READ = 0x9,
};
enum aux_request {
DPCD_READ,
DPCD_WRITE,
I2C_RAW_READ,
I2C_RAW_WRITE,
I2C_RAW_READ_AND_STOP,
I2C_RAW_WRITE_AND_STOP,
};
/* Backlight configuration */
#define DP_BACKLIGHT_MODE_SET 0x721
#define DP_BACKLIGHT_CONTROL_MODE_MASK 0x3
#define DP_BACKLIGHT_CONTROL_MODE_DPCD 0x2
#define DP_DISPLAY_CONTROL_REGISTER 0x720
#define DP_BACKLIGHT_ENABLE 0x1
#define DP_BACKLIGHT_BRIGHTNESS_MSB 0x722
#define DP_AUX_MAX_PAYLOAD_BYTES 16
bool dp_aux_request_is_write(enum aux_request request);
enum i2c_over_aux dp_get_aux_cmd(enum aux_request request, uint32_t remaining_after_this);
#endif

1
src/lib/Makefile.inc
View File

@ -147,6 +147,7 @@ ramstage-$(CONFIG_BOOTSPLASH) += bootsplash.c
ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c
ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
ramstage-$(CONFIG_COVERAGE) += libgcov.c
ramstage-y += dp_aux.c
ramstage-y += edid.c
ramstage-y += edid_fill_fb.c
ramstage-y += memrange.c

41
src/lib/dp_aux.c Normal file
View File

@ -0,0 +1,41 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <delay.h>
#include <dp_aux.h>
#include <console/console.h>
#include <timer.h>
bool dp_aux_request_is_write(enum aux_request request)
{
switch (request) {
case I2C_RAW_WRITE_AND_STOP:
case I2C_RAW_WRITE:
case DPCD_WRITE:
return true;
default:
return false;
}
}
enum i2c_over_aux dp_get_aux_cmd(enum aux_request request, uint32_t remaining_after_this)
{
switch (request) {
case I2C_RAW_WRITE_AND_STOP:
if (!remaining_after_this)
return I2C_OVER_AUX_WRITE_MOT_0;
/* fallthrough */
case I2C_RAW_WRITE:
return I2C_OVER_AUX_WRITE_MOT_1;
case I2C_RAW_READ_AND_STOP:
if (!remaining_after_this)
return I2C_OVER_AUX_READ_MOT_0;
/* fallthrough */
case I2C_RAW_READ:
return I2C_OVER_AUX_READ_MOT_1;
case DPCD_WRITE:
return NATIVE_AUX_WRITE;
case DPCD_READ:
default:
return NATIVE_AUX_READ;
}
}