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storm: Initialize clock, pinmux for NAND if present on board 

This patch runs basic NAND initialization code on Proto 0.2 boards which
have been reworked for NAND. It makes sense to do this in coreboot for
two reasons:
- In general, it is reasonable for coreboot to initialize clocks and such
  in preparation for depthcharge's use. Waiting times can be pooled, and
  the initialization itself here is very fast.
- There is a kernel bug which requires that the clock is already initialized
  before the kernel loads NAND support. coreboot is a more sensible place
  to put a workaround than depthcharge because depthcharge initializes
  things lazily, but when booting from USB, depthcharge won't need to look
  at NAND.
This change involves bringing in an additional header file, ebi2.h, from U-Boot.

TEST=Booted a kernel from USB and verified that NAND came up without any
depthcharge hacks, whereas previously a USB-booted kernel would be unable
to access NAND even with the same drivers compiled in due to an initialization
failure.
BUG=chromium:403432
BRANCH=none

Change-Id: I04e99cb39d16848a6ed75fe0229b8f79bdf2e035
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9be29da5ccad9982f146ae00344f30598ef2371c
Original-Signed-off-by: Dan Ehrenberg <dehrenberg@chromium.org>
Original-Change-Id: I1760ecb4e47438311d80e34326e45578c608481c
Original-Reviewed-on: https://chromium-review.googlesource.com/225277
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9402
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Dan Ehrenberg 2014-10-23 17:46:39 -07:00 committed by Patrick Georgi
parent 886d29bcd8
commit cb3b0c5a0d
4 changed files with 105 additions and 318 deletions
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328
src/mainboard/google/storm/cdp.c
View File

@ -3,7 +3,10 @@
#include <gpio.h>
#include <soc/cdp.h>
#include <soc/ebi2.h>
#include <soc/clock.h>
#include <types.h>
#include <boardid.h>
void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count)
{
@ -16,194 +19,6 @@ void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count)
}
}
#if 0
/* Watchdog bite time set to default reset value */
#define RESET_WDT_BITE_TIME 0x31F3
/* Watchdog bark time value is ketp larger than the watchdog timeout
* of 0x31F3, effectively disabling the watchdog bark interrupt
*/
#define RESET_WDT_BARK_TIME (5 * RESET_WDT_BITE_TIME)
/*
* If SMEM is not found, we provide a value, that will prevent the
* environment from being written to random location in the flash.
*
* NAND: In the case of NAND, we do this by setting ENV_RANGE to
* zero. If ENV_RANGE < ENV_SIZE, then environment is not written.
*
* SPI Flash: In the case of SPI Flash, we do this by setting the
* flash_index to -1.
*/
loff_t board_env_offset;
loff_t board_env_range;
extern int nand_env_device;
board_ipq806x_params_t *gboard_param;
extern int ipq_gmac_eth_initialize(const char *ethaddr);
uchar ipq_def_enetaddr[6] = {0x00, 0x03, 0x7F, 0xBA, 0xDB, 0xAD};
/*******************************************************
Function description: Board specific initialization.
I/P : None
O/P : integer, 0 - no error.
********************************************************/
static board_ipq806x_params_t *get_board_param(unsigned int machid)
{
unsigned int index = 0;
for (index = 0; index < NUM_IPQ806X_BOARDS; index++) {
if (machid == board_params[index].machid)
return &board_params[index];
}
BUG_ON(index == NUM_IPQ806X_BOARDS);
printf("cdp: Invalid machine id 0x%x\n", machid);
for (;;);
}
int board_init()
{
int ret;
uint32_t start_blocks;
uint32_t size_blocks;
loff_t board_env_size;
ipq_smem_flash_info_t *sfi = &ipq_smem_flash_info;
/*
* after relocation gboard_param is reset to NULL
* initialize again
*/
gd->bd->bi_boot_params = IPQ_BOOT_PARAMS_ADDR;
gd->bd->bi_arch_number = smem_get_board_machtype();
gboard_param = get_board_param(gd->bd->bi_arch_number);
/*
* Should be inited, before env_relocate() is called,
* since env. offset is obtained from SMEM.
*/
ret = smem_ptable_init();
if (ret < 0) {
printf("cdp: SMEM init failed\n");
return ret;
}
ret = smem_get_boot_flash(&sfi->flash_type,
&sfi->flash_index,
&sfi->flash_chip_select,
&sfi->flash_block_size);
if (ret < 0) {
printf("cdp: get boot flash failed\n");
return ret;
}
if (sfi->flash_type == SMEM_BOOT_NAND_FLASH) {
nand_env_device = CONFIG_IPQ_NAND_NAND_INFO_IDX;
} else if (sfi->flash_type == SMEM_BOOT_SPI_FLASH) {
nand_env_device = CONFIG_IPQ_SPI_NAND_INFO_IDX;
} else {
printf("BUG: unsupported flash type : %d\n", sfi->flash_type);
BUG();
}
ret = smem_getpart("0:APPSBLENV", &start_blocks, &size_blocks);
if (ret < 0) {
printf("cdp: get environment part failed\n");
return ret;
}
board_env_offset = ((loff_t) sfi->flash_block_size) * start_blocks;
board_env_size = ((loff_t) sfi->flash_block_size) * size_blocks;
board_env_range = CONFIG_ENV_SIZE;
BUG_ON(board_env_size < CONFIG_ENV_SIZE);
return 0;
}
void enable_caches(void)
{
icache_enable();
/* When dcache is enabled it causes the tftp timeout CR is raised CR.No: 513868.
* disabing dcache now to make tftp to work */
#if (CONFIG_IPQ_CACHE_ENABLE == 1)
dcache_enable();
#endif
}
/*******************************************************
Function description: DRAM initialization.
I/P : None
O/P : integer, 0 - no error.
********************************************************/
int dram_init(void)
{
struct smem_ram_ptable rtable;
int i;
int mx = ARRAY_SIZE(rtable.parts);
if (smem_ram_ptable_init(&rtable) > 0) {
gd->ram_size = 0;
for (i = 0; i < mx; i++) {
if (rtable.parts[i].category == RAM_PARTITION_SDRAM
&& rtable.parts[i].type == RAM_PARTITION_SYS_MEMORY) {
gd->ram_size += rtable.parts[i].size;
}
}
gboard_param->ddr_size = gd->ram_size;
} else {
gd->ram_size = gboard_param->ddr_size;
}
return 0;
}
/*******************************************************
Function description: initi Dram Bank size
I/P : None
O/P : integer, 0 - no error.
********************************************************/
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = IPQ_KERNEL_START_ADDR;
gd->bd->bi_dram[0].size = gboard_param->ddr_size - GENERATED_IPQ_RESERVE_SIZE;
}
/**********************************************************
Function description: Display board information on console.
I/P : None
O/P : integer, 0 - no error.
**********************************************************/
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
printf("Board: %s\n", sysinfo.board_string);
return 0;
}
#endif /* CONFIG_DISPLAY_BOARDINFO */
void reset_cpu(ulong addr)
{
printf("\nResetting with watch dog!\n");
writel(0, APCS_WDT0_EN);
writel(1, APCS_WDT0_RST);
writel(RESET_WDT_BARK_TIME, APCS_WDT0_BARK_TIME);
writel(RESET_WDT_BITE_TIME, APCS_WDT0_BITE_TIME);
writel(1, APCS_WDT0_EN);
writel(1, APCS_WDT0_CPU0_WDOG_EXPIRED_ENABLE);
for(;;);
}
static void configure_nand_gpio(void)
{
/* EBI2 CS, CLE, ALE, WE, OE */
@ -230,137 +45,16 @@ static void configure_nand_gpio(void)
void board_nand_init(void)
{
struct ebi2cr_regs *ebi2_regs;
extern int ipq_spi_init(void);
if (gboard_param->flashdesc != NOR_MMC) {
if (board_id() != BOARD_ID_PROTO_0_2_NAND)
return;
ebi2_regs = (struct ebi2cr_regs *) EBI2CR_BASE;
ebi2_regs = (struct ebi2cr_regs *) EBI2CR_BASE;
nand_clock_config();
configure_nand_gpio();
nand_clock_config();
configure_nand_gpio();
/* NAND Flash is connected to CS0 */
clrsetbits_le32(&ebi2_regs->chip_select_cfg0, CS0_CFG_MASK,
CS0_CFG_SERIAL_FLASH_DEVICE);
ipq_nand_init(IPQ_NAND_LAYOUT_LINUX);
}
ipq_spi_init();
/* NAND Flash is connected to CS0 */
clrsetbits_le32(&ebi2_regs->chip_select_cfg0, CS0_CFG_MASK,
CS0_CFG_SERIAL_FLASH_DEVICE);
}
void ipq_get_part_details(void)
{
int ret, i;
uint32_t start; /* block number */
uint32_t size; /* no. of blocks */
ipq_smem_flash_info_t *smem = &ipq_smem_flash_info;
struct { char *name; ipq_part_entry_t *part; } entries[] = {
{ "0:HLOS", &smem->hlos },
{ "0:NSS0", &smem->nss[0] },
{ "0:NSS1", &smem->nss[1] },
};
for (i = 0; i < ARRAY_SIZE(entries); i++) {
ret = smem_getpart(entries[i].name, &start, &size);
if (ret < 0) {
ipq_part_entry_t *part = entries[i].part;
printf("cdp: get part failed for %s\n", entries[i].name);
part->offset = 0xBAD0FF5E;
part->size = 0xBAD0FF5E;
}
ipq_set_part_entry(smem, entries[i].part, start, size);
}
return;
}
/*
* Get the kernel partition details from SMEM and populate the,
* environment with sufficient information for the boot command to
* load and execute the kernel.
*/
int board_late_init(void)
{
unsigned int machid;
ipq_get_part_details();
/* get machine type from SMEM and set in env */
machid = gd->bd->bi_arch_number;
if (machid != 0) {
setenv_addr("machid", (void *)machid);
gd->bd->bi_arch_number = machid;
}
return 0;
}
/*
* This function is called in the very beginning.
* Retreive the machtype info from SMEM and map the board specific
* parameters. Shared memory region at Dram address 0x40400000
* contains the machine id/ board type data polulated by SBL.
*/
int board_early_init_f(void)
{
gboard_param = get_board_param(smem_get_board_machtype());
return 0;
}
/*
* Gets the ethernet address from the ART partition table and return the value
*/
int get_eth_mac_address(uchar *enetaddr, uint no_of_macs)
{
s32 ret;
u32 start_blocks;
u32 size_blocks;
u32 length = (6 * no_of_macs);
u32 flash_type;
loff_t art_offset;
if (ipq_smem_flash_info.flash_type == SMEM_BOOT_SPI_FLASH)
flash_type = CONFIG_IPQ_SPI_NAND_INFO_IDX;
else if (ipq_smem_flash_info.flash_type == SMEM_BOOT_NAND_FLASH)
flash_type = CONFIG_IPQ_NAND_NAND_INFO_IDX;
else {
printf("Unknown flash type\n");
return -EINVAL;
}
ret = smem_getpart("0:ART", &start_blocks, &size_blocks);
if (ret < 0) {
printf("No ART partition found\n");
return ret;
}
/*
* ART partition 0th position (6 * 4) 24 bytes will contain the
* 4 MAC Address. First 0-5 bytes for GMAC0, Second 6-11 bytes
* for GMAC1, 12-17 bytes for GMAC2 and 18-23 bytes for GMAC3
*/
art_offset = ((loff_t) ipq_smem_flash_info.flash_block_size * start_blocks);
ret = nand_read(&nand_info[flash_type], art_offset, &length, enetaddr);
if (ret < 0)
printf("ART partition read failed..\n");
return ret;
}
int board_eth_init(bd_t *bis)
{
int status;
ipq_gmac_common_init(gboard_param->gmac_cfg);
ipq_configure_gpio(gboard_param->gmac_gpio,
gboard_param->gmac_gpio_count);
status = ipq_gmac_init(gboard_param->gmac_cfg);
return status;
}
#endif

2
src/mainboard/google/storm/mainboard.c
View File

@ -114,6 +114,8 @@ static void mainboard_init(device_t dev)
setup_usb();
deassert_sw_reset();
setup_tpm();
/* Functionally a 0-cost no-op if NAND is not present */
board_nand_init();
}
static void mainboard_enable(device_t dev)

11
src/soc/qualcomm/ipq806x/include/soc/cdp.h
View File

@ -106,6 +106,12 @@ typedef struct {
#define IPQ_GMAC_NMACS 4
enum storm_board_id {
BOARD_ID_PROTO_0 = 0,
BOARD_ID_PROTO_0_2 = 1,
BOARD_ID_PROTO_0_2_NAND = 26,
};
/* Board specific parameters */
typedef struct {
#if 0
@ -136,4 +142,7 @@ static inline int gmac_cfg_is_valid(ipq_gmac_board_cfg_t *cfg)
unsigned int get_board_index(unsigned machid);
void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count);
#endif
void board_nand_init(void);
#endif /* _IPQ806X_CDP_H_ */

82
src/soc/qualcomm/ipq806x/include/soc/ebi2.h Normal file
View File

@ -0,0 +1,82 @@
/*
* Copyright (c) 2012 The Linux Foundation. All rights reserved.
*
* Taken from U-Boot.
*/
#ifndef __SOC_QUALCOMM_IPQ806X_EBI2_H_
#define __SOC_QUALCOMM_IPQ806X_EBI2_H_
#define EBI2CR_BASE (0x1A600000)
struct ebi2cr_regs {
uint32_t chip_select_cfg0; /* 0x00000000 */
uint32_t cfg; /* 0x00000004 */
uint32_t hw_info; /* 0x00000008 */
uint8_t reserved0[20];
uint32_t lcd_cfg0; /* 0x00000020 */
uint32_t lcd_cfg1; /* 0x00000024 */
uint8_t reserved1[8];
uint32_t arbiter_cfg; /* 0x00000030 */
uint8_t reserved2[28];
uint32_t debug_sel; /* 0x00000050 */
uint32_t crc_cfg; /* 0x00000054 */
uint32_t crc_reminder_cfg; /* 0x00000058 */
uint32_t nand_adm_mux; /* 0x0000005C */
uint32_t mutex_addr_offset; /* 0x00000060 */
uint32_t misr_value; /* 0x00000064 */
uint32_t clkon_cfg; /* 0x00000068 */
uint32_t core_clkon_cfg; /* 0x0000006C */
};
/* Register: EBI2_CHIP_SELECT_CFG0 */
#define CS7_CFG_MASK 0x00001000
#define CS7_CFG_DISABLE 0x00000000
#define CS7_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00001000
#define CS7_CFG(i) ((i) << 12)
#define CS6_CFG_MASK 0x00000800
#define CS6_CFG_DISABLE 0x00000000
#define CS6_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000800
#define CS6_CFG(i) ((i) << 11)
#define ETM_CS_CFG_MASK 0x00000400
#define ETM_CS_CFG_DISABLE 0x00000000
#define ETM_CS_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000400
#define ETM_CS_CFG(i) ((i) << 10)
#define CS5_CFG_MASK 0x00000300
#define CS5_CFG_DISABLE 0x00000000
#define CS5_CFG_LCD_DEVICE_CONNECTED 0x00000100
#define CS5_CFG_LCD_DEVICE_CHIP_ENABLE 0x00000200
#define CS5_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000300
#define CS5_CFG(i) ((i) << 8)
#define CS4_CFG_MASK 0x000000c0
#define CS4_CFG_DISABLE 0x00000000
#define CS4_CFG_LCD_DEVICE_CONNECTED 0x00000040
#define CS4_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x000000C0
#define CS4_CFG(i) ((i) << 6)
#define CS3_CFG_MASK 0x00000020
#define CS3_CFG_DISABLE 0x00000000
#define CS3_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000020
#define CS3_CFG(i) ((i) << 5)
#define CS2_CFG_MASK 0x00000010
#define CS2_CFG_DISABLE 0x00000000
#define CS2_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000010
#define CS2_CFG(i) ((i) << 4)
#define CS1_CFG_MASK 0x0000000c
#define CS1_CFG_DISABLE 0x00000000
#define CS1_CFG_SERIAL_FLASH_DEVICE 0x00000004
#define CS1_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000008
#define CS1_CFG(i) ((i) << 2)
#define CS0_CFG_MASK 0x00000003
#define CS0_CFG_DISABLE 0x00000000
#define CS0_CFG_SERIAL_FLASH_DEVICE 0x00000001
#define CS0_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000002
#define CS0_CFG(i) ((i) << 0)
#endif