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sb/intel/i82371eb: Fix 16-bit read/write PCI_COMMAND register 

Change-Id: Icecda127a7229c1410c73a6fdd0898430f7eceb2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40809
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS 2020-04-28 19:55:10 +02:00 committed by Patrick Georgi
parent 729c0695e5
commit cb4672885e
1 changed files with 1 additions and 3 deletions
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4
src/southbridge/intel/i82371eb/isa.c
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@ -27,9 +27,7 @@ static void isa_init(struct device *dev)
/*
* Enable special cycles, needed for soft poweroff.
*/
reg32 = pci_read_config16(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_SPECIAL;
pci_write_config16(dev, PCI_COMMAND, reg32);
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SPECIAL);
/*
* The PIIX4 can support the full ISA bus, or the Extended I/O (EIO)