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cpu/intel/smm: Make sure SMRR base is aligned to SMRR size 

If TSEG_BASE is not TSEG_SIZE aligned the SMRR settings are invalid, therefore
guard against this.

Change-Id: I48f55cdac5f4b16b9a8d7a8ef3a84918e756e315
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Arthur Heymans 2018-08-06 12:10:10 +02:00 committed by Patrick Georgi
parent 60828b7fa9
commit cb5304bc0a
1 changed files with 19 additions and 13 deletions
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32
src/cpu/intel/smm/gen1/smmrelocate.c
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@ -160,20 +160,26 @@ static void fill_in_relocation_params(struct smm_relocation_params *params)
if (IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM)) if (IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM))
params->smram_size -= CONFIG_SMM_RESERVED_SIZE; params->smram_size -= CONFIG_SMM_RESERVED_SIZE;
/* SMRR has 32-bits of valid address aligned to 4KiB. */ if (IS_ALIGNED(tsegmb, tseg_size)) {
struct cpuinfo_x86 c; /* SMRR has 32-bits of valid address aligned to 4KiB. */
struct cpuinfo_x86 c;
/* On model_6fx and model_1067x bits [0:11] on smrr_base are reserved */ /* On model_6fx and model_1067x bits [0:11] on smrr_base
get_fms(&c, cpuid_eax(1)); are reserved */
if (c.x86 == 6 && (c.x86_model == 0xf || c.x86_model == 0x17)) get_fms(&c, cpuid_eax(1));
params->smrr_base.lo = (params->smram_base & rmask); if (c.x86 == 6 && (c.x86_model == 0xf || c.x86_model == 0x17))
else params->smrr_base.lo = (params->smram_base & rmask);
params->smrr_base.lo = (params->smram_base & rmask) else
| MTRR_TYPE_WRBACK; params->smrr_base.lo = (params->smram_base & rmask)
params->smrr_base.hi = 0; | MTRR_TYPE_WRBACK;
params->smrr_mask.lo = (~(tseg_size - 1) & rmask) params->smrr_base.hi = 0;
| MTRR_PHYS_MASK_VALID; params->smrr_mask.lo = (~(tseg_size - 1) & rmask)
params->smrr_mask.hi = 0; | MTRR_PHYS_MASK_VALID;
params->smrr_mask.hi = 0;
} else {
printk(BIOS_WARNING,
"TSEG base not aligned with TSEG SIZE! Not setting SMRR\n");
}
} }
static int install_relocation_handler(int *apic_id_map, int num_cpus, static int install_relocation_handler(int *apic_id_map, int num_cpus,