cpu/intel/smm: Make sure SMRR base is aligned to SMRR size
If TSEG_BASE is not TSEG_SIZE aligned the SMRR settings are invalid, therefore guard against this. Change-Id: I48f55cdac5f4b16b9a8d7a8ef3a84918e756e315 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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@ -160,20 +160,26 @@ static void fill_in_relocation_params(struct smm_relocation_params *params)
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if (IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM))
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params->smram_size -= CONFIG_SMM_RESERVED_SIZE;
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/* SMRR has 32-bits of valid address aligned to 4KiB. */
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struct cpuinfo_x86 c;
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if (IS_ALIGNED(tsegmb, tseg_size)) {
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/* SMRR has 32-bits of valid address aligned to 4KiB. */
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struct cpuinfo_x86 c;
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/* On model_6fx and model_1067x bits [0:11] on smrr_base are reserved */
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get_fms(&c, cpuid_eax(1));
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if (c.x86 == 6 && (c.x86_model == 0xf || c.x86_model == 0x17))
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params->smrr_base.lo = (params->smram_base & rmask);
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else
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params->smrr_base.lo = (params->smram_base & rmask)
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| MTRR_TYPE_WRBACK;
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params->smrr_base.hi = 0;
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params->smrr_mask.lo = (~(tseg_size - 1) & rmask)
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| MTRR_PHYS_MASK_VALID;
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params->smrr_mask.hi = 0;
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/* On model_6fx and model_1067x bits [0:11] on smrr_base
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are reserved */
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get_fms(&c, cpuid_eax(1));
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if (c.x86 == 6 && (c.x86_model == 0xf || c.x86_model == 0x17))
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params->smrr_base.lo = (params->smram_base & rmask);
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else
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params->smrr_base.lo = (params->smram_base & rmask)
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| MTRR_TYPE_WRBACK;
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params->smrr_base.hi = 0;
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params->smrr_mask.lo = (~(tseg_size - 1) & rmask)
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| MTRR_PHYS_MASK_VALID;
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params->smrr_mask.hi = 0;
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} else {
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printk(BIOS_WARNING,
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"TSEG base not aligned with TSEG SIZE! Not setting SMRR\n");
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}
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}
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static int install_relocation_handler(int *apic_id_map, int num_cpus,
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