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mb/intel/coffeelake_rvp: Update mainboard UART Kconfig 

Update mainboard UART Kconfig for Whiskylake RVP.

TEST=Build and test on Whiskylake RVP.
By default we can still get console from cbmem, and
enable CONSOLE_SERIAL can get logs from UART port2.
Select other Coffeelake RVPs and check CONSOLE_SERIAL is enabled.

Change-Id: Ic56c019a12b467e5bede5648098d3fb82b56ba7e
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-on: https://review.coreboot.org/c/30861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
This commit is contained in:
Wonkyu Kim 2019-01-11 13:46:18 -08:00 committed by Patrick Georgi
parent c6ff1ac29e
commit cb5323415e
1 changed files with 6 additions and 0 deletions
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6
src/mainboard/intel/coffeelake_rvp/Kconfig
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@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS
select GENERIC_SPD_BIN select GENERIC_SPD_BIN
select HAVE_ACPI_RESUME select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES select HAVE_ACPI_TABLES
select INTEL_LPSS_UART_FOR_CONSOLE if BOARD_INTEL_WHISKEYLAKE_RVP
select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_CHROMEOS
select GENERIC_SPD_BIN select GENERIC_SPD_BIN
select DRIVERS_I2C_HID select DRIVERS_I2C_HID
@ -48,6 +49,11 @@ config MAX_CPUS
default 12 if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 default 12 if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8
default 8 default 8
config UART_FOR_CONSOLE
int
default 2 if BOARD_INTEL_WHISKEYLAKE_RVP
default 0
config DEVICETREE config DEVICETREE
string string
default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"