Factor out print_conf() from Geode LX mainboard directories. The
following mainboard files had identical Geode LX specific print_conf() implementations: mainboard/amd/db800/mainboard.c mainboard/amd/norwich/mainboard.c mainboard/digitallogic/msm800sev/mainboard.c mainboard/pcengines/alix1c/mainboard.c Move print_conf() to northbridge/amd/lx/northbridge.c where it belongs. Add a copyright notice to mainboard/digitallogic/msm800sev/mainboard.c. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Carl-Daniel Hailfinger
parent
10aca3cae2
commit
cb5c9fb9e3
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@ -19,162 +19,8 @@
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#include <console/console.h>
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#include <device/device.h>
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#include <arch/io.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/lxdef.h>
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#include <device/pci_def.h>
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#include "../../../southbridge/amd/cs5536/cs5536.h"
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#include "chip.h"
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/* Print the platform configuration - do before PCI init or it will not
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* work right.
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*/
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void print_conf(void)
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{
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#if DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
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int i;
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unsigned long iol;
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msr_t msr;
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int cpu_msr_defs[] = { CPU_BC_L2_CONF, CPU_IM_CONFIG, CPU_DM_CONFIG0,
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CPU_RCONF_DEFAULT, CPU_RCONF_BYPASS, CPU_RCONF_A0_BF,
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CPU_RCONF_C0_DF, CPU_RCONF_E0_FF, CPU_RCONF_SMM, CPU_RCONF_DMM,
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GLCP_DELAY_CONTROLS, GL_END
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};
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int gliu0_msr_defs[] = { MSR_GLIU0_BASE1, MSR_GLIU0_BASE2,
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MSR_GLIU0_BASE4, MSR_GLIU0_BASE5, MSR_GLIU0_BASE6,
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GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM,
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GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2,
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MSR_GLIU0_SHADOW, GLIU0_IOD_BM_0, GLIU0_IOD_BM_1,
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GLIU0_IOD_BM_2, GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2,
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GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5,
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GLIU0_GLD_MSR_COH, GL_END
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};
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int gliu1_msr_defs[] = { MSR_GLIU1_BASE1, MSR_GLIU1_BASE2,
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MSR_GLIU1_BASE3, MSR_GLIU1_BASE4, MSR_GLIU1_BASE5,
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MSR_GLIU1_BASE6, MSR_GLIU1_BASE7, MSR_GLIU1_BASE8,
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MSR_GLIU1_BASE9, MSR_GLIU1_BASE10, GLIU1_P2D_R_0,
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GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3, MSR_GLIU1_SHADOW,
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GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2, GLIU1_IOD_SC_0,
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GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3,
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GLIU1_GLD_MSR_COH, GL_END
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};
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int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3,
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CPU_RCONF4, CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END
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};
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int cs5536_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1,
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MDD_LEG_IO, MDD_PIN_OPT, MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH,
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MDD_IRQM_PRIM, GL_END
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};
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int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF,
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GLPCI_C0_DF, GLPCI_E0_FF, GLPCI_RC0, GLPCI_RC1, GLPCI_RC2,
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GLPCI_RC3, GLPCI_ExtMSR, GLPCI_SPARE, GL_END
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};
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int dma_msr[] = { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2,
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MDD_DMA_SHAD3, MDD_DMA_SHAD4, MDD_DMA_SHAD5, MDD_DMA_SHAD6,
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MDD_DMA_SHAD7, MDD_DMA_SHAD8, MDD_DMA_SHAD9, GL_END
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};
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printk_debug("---------- CPU ------------\n");
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for (i = 0; cpu_msr_defs[i] != GL_END; i++) {
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msr = rdmsr(cpu_msr_defs[i]);
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printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
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cpu_msr_defs[i], msr.hi, msr.lo);
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}
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printk_debug("---------- GLIU 0 ------------\n");
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for (i = 0; gliu0_msr_defs[i] != GL_END; i++) {
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msr = rdmsr(gliu0_msr_defs[i]);
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printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
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gliu0_msr_defs[i], msr.hi, msr.lo);
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}
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printk_debug("---------- GLIU 1 ------------\n");
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for (i = 0; gliu1_msr_defs[i] != GL_END; i++) {
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msr = rdmsr(gliu1_msr_defs[i]);
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printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
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gliu1_msr_defs[i], msr.hi, msr.lo);
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}
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printk_debug("---------- RCONF ------------\n");
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for (i = 0; rconf_msr[i] != GL_END; i++) {
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msr = rdmsr(rconf_msr[i]);
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printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i],
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msr.hi, msr.lo);
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}
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printk_debug("---------- VARIA ------------\n");
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msr = rdmsr(0x51300010);
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printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi,
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msr.lo);
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msr = rdmsr(0x51400015);
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printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi,
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msr.lo);
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printk_debug("---------- DIVIL IRQ ------------\n");
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msr = rdmsr(MDD_IRQM_YLOW);
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printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi,
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msr.lo);
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msr = rdmsr(MDD_IRQM_YHIGH);
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printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH,
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msr.hi, msr.lo);
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msr = rdmsr(MDD_IRQM_ZLOW);
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printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi,
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msr.lo);
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msr = rdmsr(MDD_IRQM_ZHIGH);
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printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH,
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msr.hi, msr.lo);
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printk_debug("---------- PCI ------------\n");
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for (i = 0; pci_msr[i] != GL_END; i++) {
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msr = rdmsr(pci_msr[i]);
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printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i],
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msr.hi, msr.lo);
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}
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printk_debug("---------- LPC/UART DMA ------------\n");
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for (i = 0; dma_msr[i] != GL_END; i++) {
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msr = rdmsr(dma_msr[i]);
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printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i],
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msr.hi, msr.lo);
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}
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printk_debug("---------- CS5536 ------------\n");
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for (i = 0; cs5536_msr[i] != GL_END; i++) {
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msr = rdmsr(cs5536_msr[i]);
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printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i],
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msr.hi, msr.lo);
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}
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iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
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printk_debug("IOR 0x%08X is now 0x%08X\n",
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GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol);
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iol = inl(GPIOL_EVENTS_ENABLE);
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printk_debug("IOR 0x%08X is now 0x%08X\n",
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GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol);
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iol = inl(GPIOL_INPUT_INVERT_ENABLE);
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printk_debug("IOR 0x%08X is now 0x%08X\n",
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GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol);
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iol = inl(GPIO_MAPPER_X);
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printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIO_MAPPER_X,
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iol);
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#endif //DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
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}
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static void init(struct device *dev)
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{
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printk_debug("AMD DB800 ENTER %s\n", __FUNCTION__);
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@ -189,5 +35,4 @@ static void enable_dev(struct device *dev)
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struct chip_operations mainboard_amd_db800_ops = {
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CHIP_NAME("AMD DB800 Mainboard")
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.enable_dev = enable_dev,
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};
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@ -19,162 +19,8 @@
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#include <console/console.h>
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#include <device/device.h>
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#include <arch/io.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/lxdef.h>
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#include <device/pci_def.h>
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#include "../../../southbridge/amd/cs5536/cs5536.h"
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#include "chip.h"
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/* Print the platform configuration - do before PCI init or it will not
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* work right.
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*/
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void print_conf(void)
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{
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#if DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
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int i;
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unsigned long iol;
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msr_t msr;
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int cpu_msr_defs[] = { CPU_BC_L2_CONF, CPU_IM_CONFIG, CPU_DM_CONFIG0,
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CPU_RCONF_DEFAULT, CPU_RCONF_BYPASS, CPU_RCONF_A0_BF,
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CPU_RCONF_C0_DF, CPU_RCONF_E0_FF, CPU_RCONF_SMM, CPU_RCONF_DMM,
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GLCP_DELAY_CONTROLS, GL_END
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};
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int gliu0_msr_defs[] = { MSR_GLIU0_BASE1, MSR_GLIU0_BASE2,
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MSR_GLIU0_BASE4, MSR_GLIU0_BASE5, MSR_GLIU0_BASE6,
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GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM,
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GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2,
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MSR_GLIU0_SHADOW, GLIU0_IOD_BM_0, GLIU0_IOD_BM_1,
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GLIU0_IOD_BM_2, GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2,
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GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5,
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GLIU0_GLD_MSR_COH, GL_END
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};
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int gliu1_msr_defs[] = { MSR_GLIU1_BASE1, MSR_GLIU1_BASE2,
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MSR_GLIU1_BASE3, MSR_GLIU1_BASE4, MSR_GLIU1_BASE5,
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MSR_GLIU1_BASE6, MSR_GLIU1_BASE7, MSR_GLIU1_BASE8,
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MSR_GLIU1_BASE9, MSR_GLIU1_BASE10, GLIU1_P2D_R_0,
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GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3, MSR_GLIU1_SHADOW,
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GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2, GLIU1_IOD_SC_0,
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GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3,
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GLIU1_GLD_MSR_COH, GL_END
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};
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int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3,
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CPU_RCONF4, CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END
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};
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int cs5536_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1,
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MDD_LEG_IO, MDD_PIN_OPT, MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH,
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MDD_IRQM_PRIM, GL_END
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};
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int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF,
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GLPCI_C0_DF, GLPCI_E0_FF, GLPCI_RC0, GLPCI_RC1, GLPCI_RC2,
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GLPCI_RC3, GLPCI_ExtMSR, GLPCI_SPARE, GL_END
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};
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int dma_msr[] = { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2,
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MDD_DMA_SHAD3, MDD_DMA_SHAD4, MDD_DMA_SHAD5, MDD_DMA_SHAD6,
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MDD_DMA_SHAD7, MDD_DMA_SHAD8, MDD_DMA_SHAD9, GL_END
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};
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printk_debug("---------- CPU ------------\n");
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for (i = 0; cpu_msr_defs[i] != GL_END; i++) {
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msr = rdmsr(cpu_msr_defs[i]);
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printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
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cpu_msr_defs[i], msr.hi, msr.lo);
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}
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printk_debug("---------- GLIU 0 ------------\n");
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for (i = 0; gliu0_msr_defs[i] != GL_END; i++) {
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msr = rdmsr(gliu0_msr_defs[i]);
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printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
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gliu0_msr_defs[i], msr.hi, msr.lo);
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}
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printk_debug("---------- GLIU 1 ------------\n");
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for (i = 0; gliu1_msr_defs[i] != GL_END; i++) {
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msr = rdmsr(gliu1_msr_defs[i]);
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printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
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gliu1_msr_defs[i], msr.hi, msr.lo);
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}
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printk_debug("---------- RCONF ------------\n");
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for (i = 0; rconf_msr[i] != GL_END; i++) {
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msr = rdmsr(rconf_msr[i]);
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printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i],
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msr.hi, msr.lo);
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}
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printk_debug("---------- VARIA ------------\n");
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msr = rdmsr(0x51300010);
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printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi,
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msr.lo);
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msr = rdmsr(0x51400015);
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printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi,
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msr.lo);
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printk_debug("---------- DIVIL IRQ ------------\n");
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msr = rdmsr(MDD_IRQM_YLOW);
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printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi,
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msr.lo);
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msr = rdmsr(MDD_IRQM_YHIGH);
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printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH,
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msr.hi, msr.lo);
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msr = rdmsr(MDD_IRQM_ZLOW);
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printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi,
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msr.lo);
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msr = rdmsr(MDD_IRQM_ZHIGH);
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printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH,
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msr.hi, msr.lo);
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printk_debug("---------- PCI ------------\n");
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for (i = 0; pci_msr[i] != GL_END; i++) {
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msr = rdmsr(pci_msr[i]);
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printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i],
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msr.hi, msr.lo);
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}
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printk_debug("---------- LPC/UART DMA ------------\n");
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for (i = 0; dma_msr[i] != GL_END; i++) {
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msr = rdmsr(dma_msr[i]);
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printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i],
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msr.hi, msr.lo);
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}
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printk_debug("---------- CS5536 ------------\n");
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for (i = 0; cs5536_msr[i] != GL_END; i++) {
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msr = rdmsr(cs5536_msr[i]);
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printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i],
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msr.hi, msr.lo);
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}
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iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
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printk_debug("IOR 0x%08X is now 0x%08X\n",
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GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol);
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iol = inl(GPIOL_EVENTS_ENABLE);
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printk_debug("IOR 0x%08X is now 0x%08X\n",
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GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol);
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iol = inl(GPIOL_INPUT_INVERT_ENABLE);
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printk_debug("IOR 0x%08X is now 0x%08X\n",
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GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol);
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iol = inl(GPIO_MAPPER_X);
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printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIO_MAPPER_X,
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iol);
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#endif //DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
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}
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static void init(struct device *dev)
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{
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printk_debug("Norwich ENTER %s\n", __FUNCTION__);
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|
|
@ -189,5 +35,4 @@ static void enable_dev(struct device *dev)
|
|||
struct chip_operations mainboard_amd_norwich_ops = {
|
||||
CHIP_NAME("AMD Norwich Mainboard")
|
||||
.enable_dev = enable_dev,
|
||||
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,144 +1,29 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <arch/io.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/amd/lxdef.h>
|
||||
#include "../../../southbridge/amd/cs5536/cs5536.h"
|
||||
#include "chip.h"
|
||||
|
||||
/* Print the platform configuration */
|
||||
void print_conf(void) {
|
||||
#if DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
|
||||
int i;
|
||||
unsigned long iol;
|
||||
msr_t msr;
|
||||
|
||||
int cpu_msr_defs[] = { CPU_BC_L2_CONF, CPU_IM_CONFIG,
|
||||
CPU_DM_CONFIG0, CPU_RCONF_DEFAULT,
|
||||
CPU_RCONF_BYPASS, CPU_RCONF_A0_BF, CPU_RCONF_C0_DF, CPU_RCONF_E0_FF,
|
||||
CPU_RCONF_SMM, CPU_RCONF_DMM, GLCP_DELAY_CONTROLS, GL_END
|
||||
};
|
||||
|
||||
int gliu0_msr_defs[] = {MSR_GLIU0_BASE1, MSR_GLIU0_BASE2, MSR_GLIU0_BASE4, MSR_GLIU0_BASE5, MSR_GLIU0_BASE6,
|
||||
GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM,
|
||||
GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2, MSR_GLIU0_SHADOW,
|
||||
GLIU0_IOD_BM_0, GLIU0_IOD_BM_1, GLIU0_IOD_BM_2,
|
||||
GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2, GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5,
|
||||
GLIU0_GLD_MSR_COH, GL_END
|
||||
};
|
||||
|
||||
int gliu1_msr_defs[] = {MSR_GLIU1_BASE1, MSR_GLIU1_BASE2, MSR_GLIU1_BASE3, MSR_GLIU1_BASE4, MSR_GLIU1_BASE5, MSR_GLIU1_BASE6,
|
||||
MSR_GLIU1_BASE7, MSR_GLIU1_BASE8, MSR_GLIU1_BASE9, MSR_GLIU1_BASE10,
|
||||
GLIU1_P2D_R_0, GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3, MSR_GLIU1_SHADOW,
|
||||
GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2,
|
||||
GLIU1_IOD_SC_0, GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3,
|
||||
GLIU1_GLD_MSR_COH, GL_END
|
||||
};
|
||||
|
||||
int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3, CPU_RCONF4,
|
||||
CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END
|
||||
};
|
||||
|
||||
int cs5536_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, MDD_LEG_IO, MDD_PIN_OPT,
|
||||
MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH, MDD_IRQM_PRIM, GL_END
|
||||
};
|
||||
|
||||
int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF, GLPCI_C0_DF, GLPCI_E0_FF,
|
||||
GLPCI_RC0, GLPCI_RC1, GLPCI_RC2, GLPCI_RC3, GLPCI_ExtMSR, GLPCI_SPARE,
|
||||
GL_END
|
||||
};
|
||||
|
||||
int dma_msr[] = { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2, MDD_DMA_SHAD3, MDD_DMA_SHAD4,
|
||||
MDD_DMA_SHAD5, MDD_DMA_SHAD6, MDD_DMA_SHAD7, MDD_DMA_SHAD8,
|
||||
MDD_DMA_SHAD9, GL_END
|
||||
};
|
||||
|
||||
|
||||
printk_debug("---------- CPU ------------\n");
|
||||
|
||||
for(i = 0; cpu_msr_defs[i] != GL_END; i++) {
|
||||
msr = rdmsr(cpu_msr_defs[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cpu_msr_defs[i], msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- GLIU 0 ------------\n");
|
||||
|
||||
for(i = 0; gliu0_msr_defs[i] != GL_END; i++) {
|
||||
msr = rdmsr(gliu0_msr_defs[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", gliu0_msr_defs[i], msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- GLIU 1 ------------\n");
|
||||
|
||||
for(i = 0; gliu1_msr_defs[i] != GL_END; i++) {
|
||||
msr = rdmsr(gliu1_msr_defs[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", gliu1_msr_defs[i], msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- RCONF ------------\n");
|
||||
|
||||
for(i = 0; rconf_msr[i] != GL_END; i++) {
|
||||
msr = rdmsr(rconf_msr[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i], msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- VARIA ------------\n");
|
||||
msr = rdmsr(0x51300010);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi, msr.lo);
|
||||
|
||||
msr = rdmsr(0x51400015);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi, msr.lo);
|
||||
|
||||
printk_debug("---------- DIVIL IRQ ------------\n");
|
||||
msr = rdmsr(MDD_IRQM_YLOW);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi, msr.lo);
|
||||
msr = rdmsr(MDD_IRQM_YHIGH);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH, msr.hi, msr.lo);
|
||||
msr = rdmsr(MDD_IRQM_ZLOW);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi, msr.lo);
|
||||
msr = rdmsr(MDD_IRQM_ZHIGH);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH, msr.hi, msr.lo);
|
||||
|
||||
|
||||
printk_debug("---------- PCI ------------\n");
|
||||
|
||||
for(i = 0; pci_msr[i] != GL_END; i++) {
|
||||
msr = rdmsr(pci_msr[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i], msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- LPC/UART DMA ------------\n");
|
||||
|
||||
for(i = 0; dma_msr[i] != GL_END; i++) {
|
||||
msr = rdmsr(dma_msr[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i], msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- CS5536 ------------\n");
|
||||
|
||||
for(i = 0; cs5536_msr[i] != GL_END; i++) {
|
||||
msr = rdmsr(cs5536_msr[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i], msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
iol = inl(GPIOL_INPUT_ENABLE);
|
||||
printk_debug("IOR 0x%08X is now 0x%08X\n", GPIOL_INPUT_ENABLE, iol);
|
||||
iol = inl(GPIOL_EVENTS_ENABLE);
|
||||
printk_debug("IOR 0x%08X is now 0x%08X\n", GPIOL_EVENTS_ENABLE, iol);
|
||||
iol = inl(GPIOL_INPUT_INVERT_ENABLE);
|
||||
printk_debug("IOR 0x%08X is now 0x%08X\n", GPIOL_INPUT_INVERT_ENABLE, iol);
|
||||
iol = inl(GPIO_MAPPER_X);
|
||||
printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_MAPPER_X, iol);
|
||||
#endif //DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
|
||||
}
|
||||
|
||||
static void init(struct device *dev) {
|
||||
|
||||
static void init(struct device *dev)
|
||||
{
|
||||
printk_debug("MSM800SEV ENTER %s\n", __FUNCTION__);
|
||||
|
||||
printk_debug("MSM800SEV EXIT %s\n", __FUNCTION__);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -19,140 +19,8 @@
|
|||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <arch/io.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/amd/lxdef.h>
|
||||
#include "../../../southbridge/amd/cs5536/cs5536.h"
|
||||
#include "chip.h"
|
||||
|
||||
/* Print the platform configuration. */
|
||||
void print_conf(void) {
|
||||
#if DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
|
||||
int i;
|
||||
unsigned long iol;
|
||||
msr_t msr;
|
||||
|
||||
int cpu_msr_defs[] = { CPU_BC_L2_CONF, CPU_IM_CONFIG,
|
||||
CPU_DM_CONFIG0, CPU_RCONF_DEFAULT,
|
||||
CPU_RCONF_BYPASS, CPU_RCONF_A0_BF, CPU_RCONF_C0_DF, CPU_RCONF_E0_FF,
|
||||
CPU_RCONF_SMM, CPU_RCONF_DMM, GLCP_DELAY_CONTROLS, GL_END
|
||||
};
|
||||
|
||||
int gliu0_msr_defs[] = {MSR_GLIU0_BASE1, MSR_GLIU0_BASE2, MSR_GLIU0_BASE4, MSR_GLIU0_BASE5, MSR_GLIU0_BASE6,
|
||||
GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM,
|
||||
GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2, MSR_GLIU0_SHADOW,
|
||||
GLIU0_IOD_BM_0, GLIU0_IOD_BM_1, GLIU0_IOD_BM_2,
|
||||
GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2, GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5,
|
||||
GLIU0_GLD_MSR_COH, GL_END
|
||||
};
|
||||
|
||||
int gliu1_msr_defs[] = {MSR_GLIU1_BASE1, MSR_GLIU1_BASE2, MSR_GLIU1_BASE3, MSR_GLIU1_BASE4, MSR_GLIU1_BASE5, MSR_GLIU1_BASE6,
|
||||
MSR_GLIU1_BASE7, MSR_GLIU1_BASE8, MSR_GLIU1_BASE9, MSR_GLIU1_BASE10,
|
||||
GLIU1_P2D_R_0, GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3, MSR_GLIU1_SHADOW,
|
||||
GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2,
|
||||
GLIU1_IOD_SC_0, GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3,
|
||||
GLIU1_GLD_MSR_COH, GL_END
|
||||
};
|
||||
|
||||
int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3, CPU_RCONF4,
|
||||
CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END
|
||||
};
|
||||
|
||||
int cs5536_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, MDD_LEG_IO, MDD_PIN_OPT,
|
||||
MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH, MDD_IRQM_PRIM, GL_END
|
||||
};
|
||||
|
||||
int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF, GLPCI_C0_DF, GLPCI_E0_FF,
|
||||
GLPCI_RC0, GLPCI_RC1, GLPCI_RC2, GLPCI_RC3, GLPCI_ExtMSR, GLPCI_SPARE,
|
||||
GL_END
|
||||
};
|
||||
|
||||
int dma_msr[] = { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2, MDD_DMA_SHAD3, MDD_DMA_SHAD4,
|
||||
MDD_DMA_SHAD5, MDD_DMA_SHAD6, MDD_DMA_SHAD7, MDD_DMA_SHAD8,
|
||||
MDD_DMA_SHAD9, GL_END
|
||||
};
|
||||
|
||||
|
||||
printk_debug("---------- CPU ------------\n");
|
||||
|
||||
for(i = 0; cpu_msr_defs[i] != GL_END; i++) {
|
||||
msr = rdmsr(cpu_msr_defs[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cpu_msr_defs[i], msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- GLIU 0 ------------\n");
|
||||
|
||||
for(i = 0; gliu0_msr_defs[i] != GL_END; i++) {
|
||||
msr = rdmsr(gliu0_msr_defs[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", gliu0_msr_defs[i], msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- GLIU 1 ------------\n");
|
||||
|
||||
for(i = 0; gliu1_msr_defs[i] != GL_END; i++) {
|
||||
msr = rdmsr(gliu1_msr_defs[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", gliu1_msr_defs[i], msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- RCONF ------------\n");
|
||||
|
||||
for(i = 0; rconf_msr[i] != GL_END; i++) {
|
||||
msr = rdmsr(rconf_msr[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i], msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- VARIA ------------\n");
|
||||
msr = rdmsr(0x51300010);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi, msr.lo);
|
||||
|
||||
msr = rdmsr(0x51400015);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi, msr.lo);
|
||||
|
||||
printk_debug("---------- DIVIL IRQ ------------\n");
|
||||
msr = rdmsr(MDD_IRQM_YLOW);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi, msr.lo);
|
||||
msr = rdmsr(MDD_IRQM_YHIGH);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH, msr.hi, msr.lo);
|
||||
msr = rdmsr(MDD_IRQM_ZLOW);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi, msr.lo);
|
||||
msr = rdmsr(MDD_IRQM_ZHIGH);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH, msr.hi, msr.lo);
|
||||
|
||||
|
||||
printk_debug("---------- PCI ------------\n");
|
||||
|
||||
for(i = 0; pci_msr[i] != GL_END; i++) {
|
||||
msr = rdmsr(pci_msr[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i], msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- LPC/UART DMA ------------\n");
|
||||
|
||||
for(i = 0; dma_msr[i] != GL_END; i++) {
|
||||
msr = rdmsr(dma_msr[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i], msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- CS5536 ------------\n");
|
||||
|
||||
for(i = 0; cs5536_msr[i] != GL_END; i++) {
|
||||
msr = rdmsr(cs5536_msr[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i], msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
iol = inl(GPIOL_INPUT_ENABLE);
|
||||
printk_debug("IOR 0x%08X is now 0x%08X\n", GPIOL_INPUT_ENABLE, iol);
|
||||
iol = inl(GPIOL_EVENTS_ENABLE);
|
||||
printk_debug("IOR 0x%08X is now 0x%08X\n", GPIOL_EVENTS_ENABLE, iol);
|
||||
iol = inl(GPIOL_INPUT_INVERT_ENABLE);
|
||||
printk_debug("IOR 0x%08X is now 0x%08X\n", GPIOL_INPUT_INVERT_ENABLE, iol);
|
||||
iol = inl(GPIO_MAPPER_X);
|
||||
printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_MAPPER_X, iol);
|
||||
#endif //DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
|
||||
}
|
||||
|
||||
static void init(struct device *dev)
|
||||
{
|
||||
printk_debug("ALIX1.C ENTER %s\n", __FUNCTION__);
|
||||
|
|
|
|||
|
|
@ -34,6 +34,8 @@
|
|||
#include <cpu/amd/vr.h>
|
||||
#include "chip.h"
|
||||
#include "northbridge.h"
|
||||
#include "../../../southbridge/amd/cs5536/cs5536.h"
|
||||
|
||||
|
||||
/* here is programming for the various MSRs.*/
|
||||
#define IM_QWAIT 0x100000
|
||||
|
|
@ -76,7 +78,6 @@
|
|||
extern void graphics_init(void);
|
||||
extern void cpubug(void);
|
||||
extern void chipsetinit(void);
|
||||
extern void print_conf(void);
|
||||
extern uint32_t get_systop(void);
|
||||
|
||||
void northbridge_init_early(void);
|
||||
|
|
@ -118,6 +119,155 @@ struct msr_defaults {
|
|||
0}
|
||||
};
|
||||
|
||||
/* Print the platform configuration - do before PCI init or it will not
|
||||
* work right.
|
||||
*/
|
||||
void print_conf(void)
|
||||
{
|
||||
#if DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
|
||||
int i;
|
||||
unsigned long iol;
|
||||
msr_t msr;
|
||||
|
||||
int cpu_msr_defs[] = { CPU_BC_L2_CONF, CPU_IM_CONFIG, CPU_DM_CONFIG0,
|
||||
CPU_RCONF_DEFAULT, CPU_RCONF_BYPASS, CPU_RCONF_A0_BF,
|
||||
CPU_RCONF_C0_DF, CPU_RCONF_E0_FF, CPU_RCONF_SMM, CPU_RCONF_DMM,
|
||||
GLCP_DELAY_CONTROLS, GL_END
|
||||
};
|
||||
|
||||
int gliu0_msr_defs[] = { MSR_GLIU0_BASE1, MSR_GLIU0_BASE2,
|
||||
MSR_GLIU0_BASE4, MSR_GLIU0_BASE5, MSR_GLIU0_BASE6,
|
||||
GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM,
|
||||
GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2,
|
||||
MSR_GLIU0_SHADOW, GLIU0_IOD_BM_0, GLIU0_IOD_BM_1,
|
||||
GLIU0_IOD_BM_2, GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2,
|
||||
GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5,
|
||||
GLIU0_GLD_MSR_COH, GL_END
|
||||
};
|
||||
|
||||
int gliu1_msr_defs[] = { MSR_GLIU1_BASE1, MSR_GLIU1_BASE2,
|
||||
MSR_GLIU1_BASE3, MSR_GLIU1_BASE4, MSR_GLIU1_BASE5,
|
||||
MSR_GLIU1_BASE6, MSR_GLIU1_BASE7, MSR_GLIU1_BASE8,
|
||||
MSR_GLIU1_BASE9, MSR_GLIU1_BASE10, GLIU1_P2D_R_0,
|
||||
GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3, MSR_GLIU1_SHADOW,
|
||||
GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2, GLIU1_IOD_SC_0,
|
||||
GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3,
|
||||
GLIU1_GLD_MSR_COH, GL_END
|
||||
};
|
||||
|
||||
int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3,
|
||||
CPU_RCONF4, CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END
|
||||
};
|
||||
|
||||
int cs5536_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1,
|
||||
MDD_LEG_IO, MDD_PIN_OPT, MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH,
|
||||
MDD_IRQM_PRIM, GL_END
|
||||
};
|
||||
|
||||
int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF,
|
||||
GLPCI_C0_DF, GLPCI_E0_FF, GLPCI_RC0, GLPCI_RC1, GLPCI_RC2,
|
||||
GLPCI_RC3, GLPCI_ExtMSR, GLPCI_SPARE, GL_END
|
||||
};
|
||||
|
||||
int dma_msr[] = { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2,
|
||||
MDD_DMA_SHAD3, MDD_DMA_SHAD4, MDD_DMA_SHAD5, MDD_DMA_SHAD6,
|
||||
MDD_DMA_SHAD7, MDD_DMA_SHAD8, MDD_DMA_SHAD9, GL_END
|
||||
};
|
||||
|
||||
printk_debug("---------- CPU ------------\n");
|
||||
|
||||
for (i = 0; cpu_msr_defs[i] != GL_END; i++) {
|
||||
msr = rdmsr(cpu_msr_defs[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
|
||||
cpu_msr_defs[i], msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- GLIU 0 ------------\n");
|
||||
|
||||
for (i = 0; gliu0_msr_defs[i] != GL_END; i++) {
|
||||
msr = rdmsr(gliu0_msr_defs[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
|
||||
gliu0_msr_defs[i], msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- GLIU 1 ------------\n");
|
||||
|
||||
for (i = 0; gliu1_msr_defs[i] != GL_END; i++) {
|
||||
msr = rdmsr(gliu1_msr_defs[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
|
||||
gliu1_msr_defs[i], msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- RCONF ------------\n");
|
||||
|
||||
for (i = 0; rconf_msr[i] != GL_END; i++) {
|
||||
msr = rdmsr(rconf_msr[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i],
|
||||
msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- VARIA ------------\n");
|
||||
msr = rdmsr(0x51300010);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi,
|
||||
msr.lo);
|
||||
|
||||
msr = rdmsr(0x51400015);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi,
|
||||
msr.lo);
|
||||
|
||||
printk_debug("---------- DIVIL IRQ ------------\n");
|
||||
msr = rdmsr(MDD_IRQM_YLOW);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi,
|
||||
msr.lo);
|
||||
msr = rdmsr(MDD_IRQM_YHIGH);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH,
|
||||
msr.hi, msr.lo);
|
||||
msr = rdmsr(MDD_IRQM_ZLOW);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi,
|
||||
msr.lo);
|
||||
msr = rdmsr(MDD_IRQM_ZHIGH);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH,
|
||||
msr.hi, msr.lo);
|
||||
|
||||
printk_debug("---------- PCI ------------\n");
|
||||
|
||||
for (i = 0; pci_msr[i] != GL_END; i++) {
|
||||
msr = rdmsr(pci_msr[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i],
|
||||
msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- LPC/UART DMA ------------\n");
|
||||
|
||||
for (i = 0; dma_msr[i] != GL_END; i++) {
|
||||
msr = rdmsr(dma_msr[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i],
|
||||
msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- CS5536 ------------\n");
|
||||
|
||||
for (i = 0; cs5536_msr[i] != GL_END; i++) {
|
||||
msr = rdmsr(cs5536_msr[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i],
|
||||
msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
|
||||
printk_debug("IOR 0x%08X is now 0x%08X\n",
|
||||
GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol);
|
||||
iol = inl(GPIOL_EVENTS_ENABLE);
|
||||
printk_debug("IOR 0x%08X is now 0x%08X\n",
|
||||
GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol);
|
||||
iol = inl(GPIOL_INPUT_INVERT_ENABLE);
|
||||
printk_debug("IOR 0x%08X is now 0x%08X\n",
|
||||
GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol);
|
||||
iol = inl(GPIO_MAPPER_X);
|
||||
printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIO_MAPPER_X,
|
||||
iol);
|
||||
#endif //DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
|
||||
}
|
||||
|
||||
/* todo: add a resource record. We don't do this here because this may be called when
|
||||
* very little of the platform is actually working.
|
||||
*/
|
||||
|
|
|
|||
Loading…
Reference in New Issue