Falco/Slippy: Patch to remove redundant graphics initializations
gma_fui_init repeats the initializations already performed in gma_setup_panel. These redundant initializations reset any gtt settings done before this call. Hence, they had to be done again after call to gma_fui_init. However, the call gma_fui_init is not required at all. Does not affect the behavior of suspend/resume. Old-Change-Id: Idfb9f9930624694b878ddc0fe8648b3c8dd80e55 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65997 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit c376aea1b89c9a829874d5c657693993a3bb1f13) Falco/Slippy: Patch to fix garbage on screen during graphics initialization in normal mode Depending on the init_fb parameter: 1) For normal mode, first page is filled with zeroes and setgtt is used make all GTT entries point to this same page 2) For developer/recovery mode, we init the gtt to consecutive pages Old-Change-Id: I281b0b7efe01f7892e98b19ff9a63c04b087bd2c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65633 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 97c99dfe52ef3a87d387fdbf27ad3a28ad81c722) Squashed two graphics related commits for Falco/Slippy. Change-Id: I7ddb92672c026fe66f9fb0caba9d8fdc3f8a9d0a Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6536 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Furquan Shaikh
Patrick Georgi
parent
0f027e421a
commit
cb61ea7a13
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@ -43,6 +43,7 @@
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#include <cpu/x86/msr.h>
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#include <edid.h>
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#include <drivers/intel/gma/i915.h>
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/*
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* Here is the rough outline of how we bring up the display:
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* 1. Upon power-on Sink generates a hot plug detection pulse thru HPD
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@ -160,87 +161,6 @@ static void palette(void)
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}
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}
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/* this is code known to be needed for FUI, and useful
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* but not essential otherwise. At some point, we hope,
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* it's always going to be on. It gets the chip
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* into a known good state
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* -- including turning on the power well --
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* which we're not sure is being done correctly.
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* Does it belong here? It belongs somewhere in the
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* northbridge, that we know.
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*/
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static void gma_fui_init(int noisy)
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{
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printk(BIOS_SPEW, "pci dev(0x0,0x2,0x0,0x8)");
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printk(BIOS_SPEW, "pci dev(0x0,0x1f,0x0,0x10)");
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printk(BIOS_SPEW, "pci dev(0x0,0x2,0x0,0x0)");
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printk(BIOS_SPEW, "pci dev(0x0,0x2,0x0,0x2)");
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printk(BIOS_SPEW, "pci dev(0x0,0x1f,0x0,0x0)");
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printk(BIOS_SPEW, "pci dev(0x0,0x1f,0x0,0x2)");
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io_i915_write32(0x80000000,0x45400);
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intel_dp_wait_reg(0x00045400, 0xc0000000);
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printk(BIOS_SPEW, "pci dev(0x0,0x0,0x0,0x14)");
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printk(BIOS_SPEW, "pci dev(0x0,0x2,0x0,0x17)");
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printk(BIOS_SPEW, "pci dev(0x0,0x2,0x0,0x18)");
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io_i915_write32(0x00000000,_CURACNTR);
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io_i915_write32((/* DISPPLANE_SEL_PIPE(0=A,1=B) */0x0<<24)|0x00000000,_DSPACNTR);
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io_i915_write32(0x00000000,_DSPBCNTR);
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io_i915_write32(0x8000298e,CPU_VGACNTRL);
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io_i915_write32(0x00000000,_DSPASIZE+0xc);
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io_i915_write32(0x00000000,_DSPBSURF);
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io_i915_write32( DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x00000091,DP_A);
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io_i915_write32(0x00200090,_FDI_RXA_MISC);
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io_i915_write32(0x0a000000,_FDI_RXA_MISC);
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io_i915_write32(0x00000070,0x46408);
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io_i915_write32(0x04000000,0x42090);
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io_i915_write32(0x00000000,0x9840);
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io_i915_write32(0xa4000000,0x42090);
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io_i915_write32(0x00001000,SOUTH_DSPCLK_GATE_D);
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io_i915_write32(0x00004000,0x42080);
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io_i915_write32(0x00ffffff,0x64f80);
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io_i915_write32(0x0007000e,0x64f84);
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io_i915_write32(0x00d75fff,0x64f88);
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io_i915_write32(0x000f000a,0x64f8c);
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io_i915_write32(0x00c30fff,0x64f90);
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io_i915_write32(0x00060006,0x64f94);
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io_i915_write32(0x00aaafff,0x64f98);
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io_i915_write32(0x001e0000,0x64f9c);
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io_i915_write32(0x00ffffff,0x64fa0);
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io_i915_write32(0x000f000a,0x64fa4);
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io_i915_write32(0x00d75fff,0x64fa8);
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io_i915_write32(0x00160004,0x64fac);
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io_i915_write32(0x00c30fff,0x64fb0);
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io_i915_write32(0x001e0000,0x64fb4);
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io_i915_write32(0x00ffffff,0x64fb8);
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io_i915_write32(0x00060006,0x64fbc);
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io_i915_write32(0x00d75fff,0x64fc0);
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io_i915_write32(0x001e0000,0x64fc4);
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io_i915_write32(0x00ffffff,DDI_BUF_TRANS_A);
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io_i915_write32(0x0006000e,DDI_BUF_TRANS_A+0x4);
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io_i915_write32(0x00d75fff,DDI_BUF_TRANS_A+0x8);
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io_i915_write32(0x0005000a,DDI_BUF_TRANS_A+0xc);
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io_i915_write32(0x00c30fff,DDI_BUF_TRANS_A+0x10);
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io_i915_write32(0x00040006,DDI_BUF_TRANS_A+0x14);
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io_i915_write32(0x80aaafff,DDI_BUF_TRANS_A+0x18);
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io_i915_write32(0x000b0000,DDI_BUF_TRANS_A+0x1c);
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io_i915_write32(0x00ffffff,DDI_BUF_TRANS_A+0x20);
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io_i915_write32(0x0005000a,DDI_BUF_TRANS_A+0x24);
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io_i915_write32(0x00d75fff,DDI_BUF_TRANS_A+0x28);
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io_i915_write32(0x000c0004,DDI_BUF_TRANS_A+0x2c);
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io_i915_write32(0x80c30fff,DDI_BUF_TRANS_A+0x30);
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io_i915_write32(0x000b0000,DDI_BUF_TRANS_A+0x34);
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io_i915_write32(0x00ffffff,DDI_BUF_TRANS_A+0x38);
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io_i915_write32(0x00040006,DDI_BUF_TRANS_A+0x3c);
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io_i915_write32(0x80d75fff,DDI_BUF_TRANS_A+0x40);
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io_i915_write32(0x000b0000,DDI_BUF_TRANS_A+0x44);
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io_i915_write32( DIGITAL_PORTA_HOTPLUG_ENABLE |0x00000010,DIGITAL_PORT_HOTPLUG_CNTRL);
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io_i915_write32( PORTD_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |0x10100010,SDEISR+0x30);
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io_i915_write32((PCH_PP_UNLOCK&0xabcd0000)| EDP_FORCE_VDD |0xabcd0008,PCH_PP_CONTROL);
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mdelay(200);
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io_i915_write32(0x0004af06,PCH_PP_DIVISOR);
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/* we may need more but let's see. */
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}
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void dp_init_dim_regs(struct intel_dp *dp);
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void dp_init_dim_regs(struct intel_dp *dp)
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{
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@ -351,10 +271,9 @@ void mainboard_train_link(struct intel_dp *intel_dp)
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}
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int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio,
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unsigned int gfx);
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unsigned int gfx, unsigned int init_fb);
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int i915lightup(unsigned int pphysbase, unsigned int piobase,
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unsigned int pmmio, unsigned int pgfx)
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unsigned int pmmio, unsigned int pgfx, unsigned int init_fb)
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{
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int must_cycle_power = 0;
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struct intel_dp adp, *dp = &adp;
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@ -377,6 +296,7 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase,
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void runio(struct intel_dp *dp);
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void runlinux(struct intel_dp *dp);
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dp->gen = 8; // ??
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dp->is_haswell = 1;
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dp->DP = 0x2;
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@ -396,7 +316,17 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase,
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dp->aux_clock_divider = 0xe1;
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dp->precharge = 3;
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gma_fui_init(0);
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/* 1. Normal mode: Set the first page to zero and make
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all GTT entries point to the same page
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2. Developer/Recovery mode: We do not zero out all
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the pages pointed to by GTT in order to avoid wasting time */
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if (init_fb)
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setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096);
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else {
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setgtt(0, FRAME_BUFFER_PAGES, physbase, 0);
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memset((void*)graphics, 0, 4096);
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}
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//intel_prepare_ddi_buffers(0, 0);
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//ironlake_edp_panel_vdd_on(dp);
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dp->address = 0x50;
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@ -426,9 +356,8 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase,
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io_i915_write32(0x00000021,0x6f410);
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runio(dp);
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palette();
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setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096);
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palette();
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pixels = dp->edid.ha * (dp->edid.va-4) * 4;
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printk(BIOS_SPEW, "ha=%d, va=%d\n",dp->edid.ha, dp->edid.va);
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@ -30,6 +30,10 @@
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#include "chip.h"
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#include "haswell.h"
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#if CONFIG_CHROMEOS
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#include <vendorcode/google/chromeos/chromeos.h>
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#endif
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struct gt_reg {
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u32 reg;
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u32 andmask;
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@ -403,12 +407,18 @@ static void gma_func0_init(struct device *dev)
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#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
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printk(BIOS_SPEW, "NATIVE graphics, run native enable\n");
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u32 iobase, mmiobase, physbase;
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/* Default set to 1 since it might be required for
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stuff like seabios */
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unsigned int init_fb = 1;
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iobase = dev->resource_list[2].base;
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mmiobase = dev->resource_list[0].base;
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physbase = pci_read_config32(dev, 0x5c) & ~0xf;
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int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx);
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lightup_ok = i915lightup(physbase, iobase, mmiobase, graphics_base);
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#ifdef CONFIG_CHROMEOS
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init_fb = developer_mode_enabled() || recovery_mode_enabled();
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#endif
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int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio,
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unsigned int gfx, unsigned int init_fb);
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lightup_ok = i915lightup(physbase, iobase, mmiobase, graphics_base, init_fb);
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if (lightup_ok)
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gfx_set_init_done(1);
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#endif
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