From cb7d6a19bb4fafaeb52e0ad3b6683dc3ac5e242e Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Fri, 25 Nov 2016 15:40:49 +0100 Subject: [PATCH] nb/intel/sandybridge/raminit: Add default values Add 100 Mhz reflock default values for Ivybridge. Some values are extracted from MRC, those marked as guessed needs to be verified. Tested on Lenovo T430 (Intel IvyBridge) and DDR3-1800. Change-Id: Ife7f899b5fea02827ad998e9e8ab10ecaef61191 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/17609 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- .../intel/sandybridge/raminit_ivy.c | 51 +++++++++++++++++-- 1 file changed, 48 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c index 5cdfe8971b..97bf50b52d 100644 --- a/src/northbridge/intel/sandybridge/raminit_ivy.c +++ b/src/northbridge/intel/sandybridge/raminit_ivy.c @@ -292,10 +292,28 @@ static void dram_timing(ramctr_timing * ctrl) u8 val; u32 val32; - /* Maximum supported DDR3 frequency is 1066MHz (DDR3 2133) so make sure - * we cap it if we have faster DIMMs. + /* Maximum supported DDR3 frequency is 1400MHz (DDR3 2800). + * We cap it at 1200Mhz (DDR3 2400). * Then, align it to the closest JEDEC standard frequency */ - if (ctrl->tCK <= TCK_1066MHZ) { + if (ctrl->tCK <= TCK_1200MHZ) { + ctrl->tCK = TCK_1200MHZ; + ctrl->edge_offset[0] = 18; //XXX: guessed + ctrl->edge_offset[1] = 8; + ctrl->edge_offset[2] = 8; + ctrl->timC_offset[0] = 20; //XXX: guessed + ctrl->timC_offset[1] = 8; + ctrl->timC_offset[2] = 8; + ctrl->reg_320c_range_threshold = 10; + } else if (ctrl->tCK <= TCK_1100MHZ) { + ctrl->tCK = TCK_1100MHZ; + ctrl->edge_offset[0] = 17; //XXX: guessed + ctrl->edge_offset[1] = 7; + ctrl->edge_offset[2] = 7; + ctrl->timC_offset[0] = 19; //XXX: guessed + ctrl->timC_offset[1] = 7; + ctrl->timC_offset[2] = 7; + ctrl->reg_320c_range_threshold = 13; + } else if (ctrl->tCK <= TCK_1066MHZ) { ctrl->tCK = TCK_1066MHZ; ctrl->edge_offset[0] = 16; ctrl->edge_offset[1] = 7; @@ -304,6 +322,15 @@ static void dram_timing(ramctr_timing * ctrl) ctrl->timC_offset[1] = 7; ctrl->timC_offset[2] = 7; ctrl->reg_320c_range_threshold = 13; + } else if (ctrl->tCK <= TCK_1000MHZ) { + ctrl->tCK = TCK_1000MHZ; + ctrl->edge_offset[0] = 15; //XXX: guessed + ctrl->edge_offset[1] = 6; + ctrl->edge_offset[2] = 6; + ctrl->timC_offset[0] = 17; //XXX: guessed + ctrl->timC_offset[1] = 6; + ctrl->timC_offset[2] = 6; + ctrl->reg_320c_range_threshold = 13; } else if (ctrl->tCK <= TCK_933MHZ) { ctrl->tCK = TCK_933MHZ; ctrl->edge_offset[0] = 14; @@ -313,6 +340,15 @@ static void dram_timing(ramctr_timing * ctrl) ctrl->timC_offset[1] = 6; ctrl->timC_offset[2] = 6; ctrl->reg_320c_range_threshold = 15; + } else if (ctrl->tCK <= TCK_900MHZ) { + ctrl->tCK = TCK_900MHZ; + ctrl->edge_offset[0] = 14; //XXX: guessed + ctrl->edge_offset[1] = 6; + ctrl->edge_offset[2] = 6; + ctrl->timC_offset[0] = 15; //XXX: guessed + ctrl->timC_offset[1] = 6; + ctrl->timC_offset[2] = 6; + ctrl->reg_320c_range_threshold = 12; } else if (ctrl->tCK <= TCK_800MHZ) { ctrl->tCK = TCK_800MHZ; ctrl->edge_offset[0] = 13; @@ -322,6 +358,15 @@ static void dram_timing(ramctr_timing * ctrl) ctrl->timC_offset[1] = 5; ctrl->timC_offset[2] = 5; ctrl->reg_320c_range_threshold = 15; + } else if (ctrl->tCK <= TCK_700MHZ) { + ctrl->tCK = TCK_700MHZ; + ctrl->edge_offset[0] = 13; //XXX: guessed + ctrl->edge_offset[1] = 5; + ctrl->edge_offset[2] = 5; + ctrl->timC_offset[0] = 14; //XXX: guessed + ctrl->timC_offset[1] = 5; + ctrl->timC_offset[2] = 5; + ctrl->reg_320c_range_threshold = 16; } else if (ctrl->tCK <= TCK_666MHZ) { ctrl->tCK = TCK_666MHZ; ctrl->edge_offset[0] = 10;