mainboard/asus/kgpe-d16: Clean up legacy PIRQ table code
Change-Id: Ib4f46944f076f1e696cf16a1e532eb8635b603c9 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13162 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
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@ -2,7 +2,7 @@
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* This file is part of the coreboot project.
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* This file is part of the coreboot project.
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*
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
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* Copyright (C) 2015 Raptor Engineering
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* it under the terms of the GNU General Public License as published by
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@ -23,6 +23,24 @@
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#include <cpu/amd/amdfam10_sysconf.h>
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#include <cpu/amd/amdfam10_sysconf.h>
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/* Free irqs are 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, and 15 */
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#define IRQBM ((1<<3)|(1<<4)|(1<<5)|(1<<6)|(1<<7)|(1<<9)|(1<<10)|(1<<11)|(1<<12)|(1<<14)|(1<<15))
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#define LNKA 1
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#define LNKB 2
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#define LNKC 3
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#define LNKD 4
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/*
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* For simplicity map LNK[E-H] to LNK[A-D].
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* This also means we are 82C596 compatible.
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* Needs 0:11.0 0x46[4] set to 0.
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*/
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#define LNKE 1
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#define LNKF 2
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#define LNKG 3
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#define LNKH 4
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static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
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static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
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u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
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u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
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u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
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u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
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@ -42,9 +60,10 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
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pirq_info->rfu = rfu;
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pirq_info->rfu = rfu;
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}
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}
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extern u8 bus_isa;
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extern u8 bus_isa;
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extern u8 bus_rs780[8];
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extern u8 bus_sr5650[14];
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extern u8 bus_sp5100[2];
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extern u8 bus_sp5100[2];
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extern unsigned long sbdn_sp5100;
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extern u32 sbdn_sp5100;
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extern u32 sbdn_sr5650;
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unsigned long write_pirq_routing_table(unsigned long addr)
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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{
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@ -71,6 +90,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
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pirq->signature = PIRQ_SIGNATURE;
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pirq->signature = PIRQ_SIGNATURE;
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pirq->version = PIRQ_VERSION;
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pirq->version = PIRQ_VERSION;
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/* Where the interrupt router resides */
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pirq->rtr_bus = bus_sp5100[0];
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pirq->rtr_bus = bus_sp5100[0];
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pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
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pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
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@ -88,8 +108,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
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/* pci bridge */
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/* pci bridge */
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write_pirq_info(pirq_info, bus_sp5100[0], ((sbdn_sp5100 + 0x14) << 3) | 4,
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write_pirq_info(pirq_info, bus_sp5100[0], ((sbdn_sp5100 + 0x14) << 3) | 4,
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0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
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LNKA, IRQBM, LNKB, IRQBM, LNKC, IRQBM, LNKD, IRQBM, 0, 0);
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0);
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pirq_info++;
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pirq_info++;
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slot_num++;
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slot_num++;
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@ -103,7 +122,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
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pirq->checksum = sum;
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pirq->checksum = sum;
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}
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}
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printk(BIOS_INFO, "write_pirq_routing_table done.\n");
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printk(BIOS_INFO, "done.\n");
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return (unsigned long)pirq_info;
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return (unsigned long)pirq_info;
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}
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}
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