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This patch fixes up a couple mistakes I made with the i82810 and mew-vw to make 

the system boot to a command line.

This patch comments out the code to set up the vga framebuffer to allow
the system to boot, without this fix the system hangs during elfboot.

The only line that is absolutely necessary to change is the SMRAM setup,
however I've commented out all vga setup to make it very obvious to both
the kernel/payload and anyone looking at the code that vga isn't
currently working. This setup might also be better handled in
northbridge.c, if it doesn't need to be done before ram init, yet
another reason to comment it all. In the future, LinuxBIOS needs to be
told that the graphics memory area, 1mb or 512kb (at the user or
developer's option), is reserved for the onchip vga, but I'm not sure if
it's taken at the top or bottom of the memory, yet. LB may also need to
set a base address for the AGP aperture and/or be told that range is
reserved as well, whether this was originally the job of the system bios
or vga bios is still a mystery. It also corrects the number of entries
in irq_tables.c, without this fix the kernel would probably complain and
hang due to unmapped IRQs.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2725 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Corey Osgood 2007-06-19 07:33:39 +00:00 committed by Uwe Hermann
parent 440113f00b
commit cbb8d8ad24
2 changed files with 13 additions and 11 deletions
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2
src/mainboard/asus/mew-vm/Options.lb
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@ -67,7 +67,7 @@ default HAVE_HARD_RESET = 0
## Build code to export a programmable irq routing table ## Build code to export a programmable irq routing table
## ##
default HAVE_PIRQ_TABLE = 1 default HAVE_PIRQ_TABLE = 1
default IRQ_SLOT_COUNT = 4 default IRQ_SLOT_COUNT = 11
## ##
## Build code to export a CMOS option table ## Build code to export a CMOS option table

22
src/northbridge/intel/i82810/raminit.c
View File

@ -69,7 +69,6 @@ SDRAM configuration functions.
static void do_ram_command(const struct mem_controller *ctrl, uint32_t command, static void do_ram_command(const struct mem_controller *ctrl, uint32_t command,
uint32_t addr_offset, uint32_t row_offset) uint32_t addr_offset, uint32_t row_offset)
{ {
int i;
uint8_t reg; uint8_t reg;
/* TODO: Support for multiple DIMMs. */ /* TODO: Support for multiple DIMMs. */
@ -242,22 +241,25 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
*/ */
/* Ideally, this should be R/W for as many ranges as possible. */ /* Ideally, this should be R/W for as many ranges as possible. */
pci_write_config8(ctrl->d0, PAM, 0x00); pci_write_config8(ctrl->d0, PAM, 0xff);
/* Enabling the VGA Framebuffer currently screws up the rest of the boot.
* Disable for now */
/* Enable 1MB framebuffer. */ /* Enable 1MB framebuffer. */
pci_write_config8(ctrl->d0, SMRAM, 0xC0); //pci_write_config8(ctrl->d0, SMRAM, 0xC0);
val = pci_read_config16(ctrl->d0, MISSC); //val = pci_read_config16(ctrl->d0, MISSC);
/* Preserve reserved bits. */ /* Preserve reserved bits. */
val &= 0xff06; //val &= 0xff06;
/* Set graphics cache window to 32MB, no power throttling. */ /* Set graphics cache window to 32MB, no power throttling. */
val |= 0x0001; //val |= 0x0001;
pci_write_config16(ctrl->d0, MISSC, val); //pci_write_config16(ctrl->d0, MISSC, val);
val = pci_read_config8(ctrl->d0, MISSC2); //val = pci_read_config8(ctrl->d0, MISSC2);
/* Enable graphics palettes and clock gating (not optional!) */ /* Enable graphics palettes and clock gating (not optional!) */
val |= 0x06; //val |= 0x06;
pci_write_config8(ctrl->d0, MISSC2, val); //pci_write_config8(ctrl->d0, MISSC2, val);
} }
/** /**