soc/intel/mtl: Keep SOC_INTEL_COMMON_BASECODE_RAMTOP for non-ChromeOS

This patch guarantees that non-ChromeOS platforms continue to enable
early caching.

ChromeOS devices, on the other hand, control this configuration through
the motherboard configuration based on the underlying SoC.

BUG=b:306677879
TEST=Enable SOC_INTEL_COMMON_BASECODE_RAMTOP for google/rex.

Change-Id: I412b2b6a807dc0f5f2632f0fbd56bd37689dead3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Subrata Banik 2023-11-14 01:36:09 +05:30 committed by Felix Held
parent 5578d91257
commit cbbfd68481
2 changed files with 3 additions and 2 deletions

View File

@ -79,7 +79,7 @@ config SOC_INTEL_METEORLAKE
select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_BLOCK_XHCI
select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
select SOC_INTEL_COMMON_BASECODE select SOC_INTEL_COMMON_BASECODE
select SOC_INTEL_COMMON_BASECODE_RAMTOP select SOC_INTEL_COMMON_BASECODE_RAMTOP if !MAINBOARD_HAS_CHROMEOS
select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_FSP_RESET
select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_PCH_CLIENT
select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_RESET

View File

@ -181,7 +181,8 @@ static void fill_tme_params(FSP_M_CONFIG *m_cfg)
m_cfg->TmeEnable = CONFIG(INTEL_TME) && is_tme_supported(); m_cfg->TmeEnable = CONFIG(INTEL_TME) && is_tme_supported();
if (!m_cfg->TmeEnable) if (!m_cfg->TmeEnable)
return; return;
m_cfg->GenerateNewTmeKey = CONFIG(TME_KEY_REGENERATION_ON_WARM_BOOT); m_cfg->GenerateNewTmeKey = CONFIG(TME_KEY_REGENERATION_ON_WARM_BOOT) &&
CONFIG(SOC_INTEL_COMMON_BASECODE_RAMTOP);
if (m_cfg->GenerateNewTmeKey) { if (m_cfg->GenerateNewTmeKey) {
uint32_t ram_top = get_ramtop_addr(); uint32_t ram_top = get_ramtop_addr();
if (!ram_top) { if (!ram_top) {