From cbca81c5946384843197c08401c4266f45fef4a2 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 20 Jan 2023 22:04:06 +0530 Subject: [PATCH] mb/google/rex: Enable SaGv This patch overrides `SaGv` FSP-M UPD to enable SaGv feature to be able to train memory (DIMM) at different frequencies. On all latest Intel based platforms SaGv is expected to be enabled to support dynamic switching of memory operating frequency. Signed-off-by: Subrata Banik Change-Id: I7cf52b966c1355c1f2bd4ae7c256fa4252a90666 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72136 Tested-by: build bot (Jenkins) Reviewed-by: Kapil Porwal Reviewed-by: Sridhar Siricilla --- src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index a3225ca111..f14699ff4e 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -20,6 +20,8 @@ chip soc/intel/meteorlake # Enable CNVi BT register "cnvi_bt_core" = "true" + register "sagv" = "SAGV_ENABLED" + register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoPci, [PchSerialIoIndexUART1] = PchSerialIoDisabled,