sb/intel/lynxpoint: Ensure that `dev->chip_info` is not null
Use either a regular null check or `config_of` to avoid bugs. Change-Id: I36a01b898c3e62423f27c2940b5f875b73e36950 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46665 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -61,7 +61,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
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ACPI_FADT_S4_RTC_WAKE |
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ACPI_FADT_PLATFORM_CLOCK;
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if (cfg->docking_supported)
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if (cfg && cfg->docking_supported)
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fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
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fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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@ -138,10 +138,8 @@ static void pch_pirq_init(struct device *dev)
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}
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}
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static void pch_gpi_routing(struct device *dev)
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static void pch_gpi_routing(struct device *dev, config_t *config)
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{
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/* Get the chip configuration */
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config_t *config = dev->chip_info;
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u32 reg32 = 0;
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/* An array would be much nicer here, or some
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@ -173,8 +171,6 @@ static void pch_power_options(struct device *dev)
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u16 reg16;
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u32 reg32;
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const char *state;
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/* Get the chip configuration */
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config_t *config = dev->chip_info;
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u16 pmbase = get_pmbase();
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int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
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int nmi_option;
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@ -243,12 +239,15 @@ static void pch_power_options(struct device *dev)
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reg16 &= ~(1 << 10); // Disable BIOS_PCI_EXP_EN for native PME
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pci_write_config16(dev, GEN_PMCON_1, reg16);
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if (dev->chip_info) {
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config_t *config = dev->chip_info;
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/*
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* Set the board's GPI routing on LynxPoint-H.
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* This is done as part of GPIO configuration on LynxPoint-LP.
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*/
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if (pch_is_lp())
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pch_gpi_routing(dev);
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pch_gpi_routing(dev, config);
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/* GPE setup based on device tree configuration */
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enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2,
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@ -256,6 +255,7 @@ static void pch_power_options(struct device *dev)
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/* SMI setup based on device tree configuration */
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enable_alt_smi(config->alt_gp_smi_en);
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}
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/* Set up power management block and determine sleep mode */
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reg32 = inl(pmbase + 0x04); // PM1_CNT
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@ -345,10 +345,10 @@ static void lpt_lp_pm_init(struct device *dev)
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/* Set RCBA CIR28 0x3A84 based on SATA port enables */
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data = 0x00001005;
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/* Port 3 and 2 disabled */
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if ((config->sata_port_map & ((1 << 3) | (1 << 2))) == 0)
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if (config && (config->sata_port_map & ((1 << 3) | (1 << 2))) == 0)
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data |= (1 << 24) | (1 << 26);
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/* Port 1 and 0 disabled */
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if ((config->sata_port_map & ((1 << 1) | (1 << 0))) == 0)
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if (config && (config->sata_port_map & ((1 << 1) | (1 << 0))) == 0)
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data |= (1 << 20) | (1 << 18);
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RCBA32(0x3a84) = data;
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@ -636,7 +636,6 @@ static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value,
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static void pch_lpc_add_io_resources(struct device *dev)
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{
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struct resource *res;
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config_t *config = dev->chip_info;
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/* Add the default claimed IO range for the LPC device. */
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res = new_resource(dev, 0);
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@ -651,11 +650,14 @@ static void pch_lpc_add_io_resources(struct device *dev)
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pch_lpc_add_io_resource(dev, get_pmbase(), 256, PMBASE);
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/* LPC Generic IO Decode range. */
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if (dev->chip_info) {
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config_t *config = dev->chip_info;
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pch_lpc_add_gen_io_resources(dev, config->gen1_dec, LPC_GEN1_DEC);
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pch_lpc_add_gen_io_resources(dev, config->gen2_dec, LPC_GEN2_DEC);
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pch_lpc_add_gen_io_resources(dev, config->gen3_dec, LPC_GEN3_DEC);
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pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC);
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}
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}
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static void pch_lpc_read_resources(struct device *dev)
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{
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@ -131,7 +131,7 @@ static void serialio_init_once(int acpi_mode)
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static void serialio_init(struct device *dev)
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{
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struct southbridge_intel_lynxpoint_config *config = dev->chip_info;
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struct southbridge_intel_lynxpoint_config *config = config_of(dev);
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struct resource *bar0, *bar1;
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int sio_index = -1;
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@ -328,7 +328,7 @@ static void usb_xhci_init(struct device *dev)
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/* Reset ports that are disabled or
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* polling before returning to the OS. */
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usb_xhci_reset_usb3(dev, 0);
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} else if (config->xhci_default) {
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} else if (config && config->xhci_default) {
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/* Route all ports to XHCI */
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apm_control(APM_CNT_ROUTE_ALL_XHCI);
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}
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