GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

sb/intel/fsp_rangeley: Get rid of device_t 

Use of device_t has been abandoned in ramstage.

Change-Id: If92825f5bdb1399f61b7eba3ae81caa9c264a554
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS 2018-05-13 13:22:58 +02:00 committed by Patrick Georgi
parent 4ccb23fe27
commit cbcdb3e754
7 changed files with 19 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
src/southbridge/intel/fsp_rangeley/lpc.c
View File

@ -114,8 +114,8 @@ static void soc_enable_serial_irqs(struct device *dev)
*/
static void write_pci_config_irqs(void)
{
device_t irq_dev;
device_t targ_dev;
struct device *irq_dev;
struct device *targ_dev;
uint8_t int_line = 0;
uint8_t original_int_pin = 0;
uint8_t new_int_pin = 0;
@ -198,7 +198,7 @@ static void write_pci_config_irqs(void)
printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n");
}
static void soc_pirq_init(device_t dev)
static void soc_pirq_init(struct device *dev)
{
int i, j;
int pirq;
@ -243,7 +243,7 @@ static void soc_pirq_init(device_t dev)
write_pci_config_irqs();
}
static void soc_power_options(device_t dev)
static void soc_power_options(struct device *dev)
{
u8 reg8;
u16 pmbase;
@ -345,7 +345,7 @@ static void lpc_init(struct device *dev)
soc_disable_smm_only_flashing(dev);
}
static void soc_lpc_read_resources(device_t dev)
static void soc_lpc_read_resources(struct device *dev)
{
struct resource *res;
config_t *config = dev->chip_info;
@ -406,17 +406,17 @@ static void soc_lpc_read_resources(device_t dev)
}
}
static void soc_lpc_enable_resources(device_t dev)
static void soc_lpc_enable_resources(struct device *dev)
{
return pci_dev_enable_resources(dev);
}
static void soc_lpc_enable(device_t dev)
static void soc_lpc_enable(struct device *dev)
{
soc_enable(dev);
}
static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
@ -427,7 +427,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
}
}
static void southbridge_inject_dsdt(device_t dev)
static void southbridge_inject_dsdt(struct device *dev)
{
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));

4
src/southbridge/intel/fsp_rangeley/sata.c
View File

@ -91,11 +91,11 @@ static void sata_init(struct device *dev)
}
static void sata_enable(device_t dev)
static void sata_enable(struct device *dev)
{
}
static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,

7
src/southbridge/intel/fsp_rangeley/smbus.c
View File

@ -25,7 +25,7 @@
#include <southbridge/intel/common/smbus.h>
#include "soc.h"
static int lsmbus_read_byte(device_t dev, u8 address)
static int lsmbus_read_byte(struct device *dev, u8 address)
{
u16 device;
struct resource *res;
@ -42,7 +42,8 @@ static struct smbus_bus_operations lops_smbus_bus = {
.read_byte = lsmbus_read_byte,
};
static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device)
static void smbus_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
@ -57,7 +58,7 @@ static struct pci_operations smbus_pci_ops = {
.set_subsystem = smbus_set_subsystem,
};
static void rangeley_smbus_read_resources(device_t dev)
static void rangeley_smbus_read_resources(struct device *dev)
{
struct resource *res;

2
src/southbridge/intel/fsp_rangeley/soc.c
View File

@ -66,7 +66,7 @@ static void soc_hide_devfn(unsigned devfn)
void soc_enable(device_t dev)
void soc_enable(struct device *dev)
{
u32 reg32;

2
src/southbridge/intel/fsp_rangeley/soc.h
View File

@ -60,7 +60,7 @@ void intel_soc_finalize_smm(void);
int soc_silicon_revision(void);
int soc_silicon_type(void);
int soc_silicon_supported(int type, int rev);
void soc_enable(device_t dev);
void soc_enable(struct device *dev);
#include <arch/acpi.h>
void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt);

2
src/southbridge/intel/fsp_rangeley/spi.c
View File

@ -343,7 +343,7 @@ void spi_init(void)
{
int ich_version = 0;
uint8_t bios_cntl;
device_t dev;
struct device *dev;
uint32_t ids;
uint16_t vendor_id, device_id;

2
src/southbridge/intel/fsp_rangeley/watchdog.c
View File

@ -25,7 +25,7 @@
void watchdog_off(void)
{
device_t dev;
struct device *dev;
u32 value, abase;
/* Turn off the watchdog. */