soc/intel/alderlake: Add PMC ACPI interface

This ACPI interface is required by e.g., the intel/common/pcie/rtd3
driver, which is used by some alderlake boards.

BUG=b:190080798
TEST=disassemble SSDT and find \_SB.PCI0.PMC.IPCS

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I59eae47e623587d35e394c9bff21481fcad2d6b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55172
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tim Wawrzynczak 2021-06-03 14:11:21 -06:00
parent 017c59096a
commit cbd2abf9b4
1 changed files with 5 additions and 0 deletions

View File

@ -12,6 +12,7 @@
#include <device/device.h> #include <device/device.h>
#include <drivers/intel/pmc_mux/chip.h> #include <drivers/intel/pmc_mux/chip.h>
#include <intelblocks/pmc.h> #include <intelblocks/pmc.h>
#include <intelblocks/pmc_ipc.h>
#include <intelblocks/pmclib.h> #include <intelblocks/pmclib.h>
#include <intelblocks/rtc.h> #include <intelblocks/rtc.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
@ -121,6 +122,10 @@ static void soc_pmc_fill_ssdt(const struct device *dev)
acpigen_write_mem32fixed(1, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE); acpigen_write_mem32fixed(1, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE);
acpigen_write_resourcetemplate_footer(); acpigen_write_resourcetemplate_footer();
/* Define IPC Write Method */
if (CONFIG(PMC_IPC_ACPI_INTERFACE))
pmc_ipc_acpi_fill_ssdt();
acpigen_pop_len(); /* PMC Device */ acpigen_pop_len(); /* PMC Device */
acpigen_pop_len(); /* Scope */ acpigen_pop_len(); /* Scope */