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soc/amd: Use spi_writeX & spi_readX for all spi accesses 

BUG=b:161366241
TEST=Build & boot Trembyle

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ied7789e9315c75174df9a686c831c5a969ce3bfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Martin Roth 2020-07-23 16:12:33 -06:00 committed by Felix Held
parent 3b8b14dc27
commit cbdd890e41
2 changed files with 12 additions and 21 deletions
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16
src/soc/amd/common/block/spi/fch_spi.c
View File

@ -10,26 +10,22 @@
static void fch_spi_set_spi100(int norm, int fast, int alt, int tpm) static void fch_spi_set_spi100(int norm, int fast, int alt, int tpm)
{ {
uintptr_t base = spi_get_bar(); spi_write16(SPI100_SPEED_CONFIG, SPI_SPEED_CFG(norm, fast, alt, tpm));
spi_write16(SPI100_ENABLE, SPI_USE_SPI100);
write16((void *)(base + SPI100_SPEED_CONFIG), SPI_SPEED_CFG(norm, fast, alt, tpm));
write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100);
} }
static void fch_spi_disable_4dw_burst(void) static void fch_spi_disable_4dw_burst(void)
{ {
uintptr_t base = spi_get_bar(); uint16_t val = spi_read16(SPI100_HOST_PREF_CONFIG);
uint16_t val = read16((void *)(base + SPI100_HOST_PREF_CONFIG));
write16((void *)(base + SPI100_HOST_PREF_CONFIG), val & ~SPI_RD4DW_EN_HOST); spi_write16(SPI100_HOST_PREF_CONFIG, val & ~SPI_RD4DW_EN_HOST);
} }
static void fch_spi_set_read_mode(u32 mode) static void fch_spi_set_read_mode(u32 mode)
{ {
uintptr_t base = spi_get_bar(); uint32_t val = spi_read32(SPI_CNTRL0) & ~SPI_READ_MODE_MASK;
uint32_t val = read32((void *)(base + SPI_CNTRL0)) & ~SPI_READ_MODE_MASK;
write32((void *)(base + SPI_CNTRL0), val | SPI_READ_MODE(mode)); spi_write32(SPI_CNTRL0, val | SPI_READ_MODE(mode));
} }
static void fch_spi_config_mb_modes(void) static void fch_spi_config_mb_modes(void)

17
src/soc/amd/stoneyridge/southbridge.c
View File

@ -267,29 +267,24 @@ static void sb_init_spi_base(void)
void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm)
{ {
uintptr_t base = spi_get_bar(); spi_write16(SPI100_SPEED_CONFIG,
write16((void *)(base + SPI100_SPEED_CONFIG),
(norm << SPI_NORM_SPEED_NEW_SH) | (norm << SPI_NORM_SPEED_NEW_SH) |
(fast << SPI_FAST_SPEED_NEW_SH) | (fast << SPI_FAST_SPEED_NEW_SH) |
(alt << SPI_ALT_SPEED_NEW_SH) | (alt << SPI_ALT_SPEED_NEW_SH) |
(tpm << SPI_TPM_SPEED_NEW_SH)); (tpm << SPI_TPM_SPEED_NEW_SH));
write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100); spi_write16(SPI100_ENABLE, SPI_USE_SPI100);
} }
void sb_disable_4dw_burst(void) void sb_disable_4dw_burst(void)
{ {
uintptr_t base = spi_get_bar(); spi_write16(SPI100_HOST_PREF_CONFIG,
write16((void *)(base + SPI100_HOST_PREF_CONFIG), spi_read16(SPI100_HOST_PREF_CONFIG) & ~SPI_RD4DW_EN_HOST);
read16((void *)(base + SPI100_HOST_PREF_CONFIG))
& ~SPI_RD4DW_EN_HOST);
} }
void sb_read_mode(u32 mode) void sb_read_mode(u32 mode)
{ {
uintptr_t base = spi_get_bar(); spi_write32(SPI_CNTRL0,
write32((void *)(base + SPI_CNTRL0), (spi_read32(SPI_CNTRL0) & ~SPI_READ_MODE_MASK) | mode);
(read32((void *)(base + SPI_CNTRL0))
& ~SPI_READ_MODE_MASK) | mode);
} }
static void setup_spread_spectrum(int *reboot) static void setup_spread_spectrum(int *reboot)