mb/google/skyrim: Enable Chrome EC

BUG=b:214413613
TEST=builds
BRANCH=none

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I15c7c482c4a5ddef22a221794b9ef03f9b7ffe05
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62046
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/skyrim/Kconfig

@@ -5,6 +5,9 @@ config BOARD_GOOGLE_BASEBOARD_SKYRIM
 
 if BOARD_GOOGLE_BASEBOARD_SKYRIM
 
+config IGNORE_IASL_MISSING_DEPENDENCY
+	def_bool y
+
 config AMD_FWM_POSITION_INDEX
 	int
 	default 3
@@ -14,9 +17,14 @@ config AMD_FWM_POSITION_INDEX
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select EC_GOOGLE_CHROMEEC
+	select EC_GOOGLE_CHROMEEC_ESPI
 	select MAINBOARD_HAS_CHROMEOS
 	select SOC_AMD_SABRINA
 
+config CHROMEOS
+	select EC_GOOGLE_CHROMEEC_SWITCHES
+
 config DEVICETREE
 	default "variants/baseboard/devicetree.cb"
 
@@ -42,7 +50,7 @@ config VARIANT_DIR
 	default "skyrim" if BOARD_GOOGLE_SKYRIM
 
 config VBOOT
-	select VBOOT_NO_BOARD_SUPPORT
+	select VBOOT_LID_SWITCH
 	select VBOOT_SEPARATE_VERSTAGE
 	select VBOOT_STARTS_IN_BOOTBLOCK
 

src/mainboard/google/skyrim/Makefile.inc

@@ -5,6 +5,7 @@ bootblock-y += bootblock.c
 romstage-y += port_descriptors.c
 
 ramstage-y += mainboard.c
+ramstage-y += ec.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 
 subdirs-y += variants/baseboard

src/mainboard/google/skyrim/chromeos.c

@@ -9,7 +9,7 @@
 void fill_lb_gpios(struct lb_gpios *gpios)
 {
 	struct lb_gpio chromeos_gpios[] = {
-		/* TODO Enable lid switch with EC */
+		{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
 		{-1, ACTIVE_HIGH, 0, "power"},
 	};
 	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));

src/mainboard/google/skyrim/dsdt.asl

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <acpi/acpi.h>
+#include <variant/ec.h>
 
 DefinitionBlock (
 	"dsdt.aml",
@@ -13,4 +14,14 @@ DefinitionBlock (
 {
 	#include <acpi/dsdt_top.asl>
 	#include <soc.asl>
+
+	/* Chrome OS Embedded Controller */
+	Scope (\_SB.PCI0.LPCB)
+	{
+		/* ACPI code for EC SuperIO functions */
+		#include <ec/google/chromeec/acpi/superio.asl>
+		/* ACPI code for EC functions */
+		#include <ec/google/chromeec/acpi/ec.asl>
+	}
+
 }

src/mainboard/google/skyrim/ec.c

@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi.h>
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include <variant/ec.h>
+
+void mainboard_ec_init(void)
+{
+	const struct google_chromeec_event_info info = {
+		.log_events = MAINBOARD_EC_LOG_EVENTS,
+		.sci_events = MAINBOARD_EC_SCI_EVENTS,
+		.s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
+		.s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
+		.s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
+	};
+
+	google_chromeec_events_init(&info, acpi_is_wakeup_s3());
+}

src/mainboard/google/skyrim/mainboard.c

@@ -3,6 +3,7 @@
 #include <baseboard/variants.h>
 #include <console/console.h>
 #include <device/device.h>
+#include <variant/ec.h>
 
 static void mainboard_configure_gpios(void)
 {
@@ -19,6 +20,7 @@ static void mainboard_configure_gpios(void)
 static void mainboard_init(void *chip_info)
 {
 	mainboard_configure_gpios();
+	mainboard_ec_init();
 }
 
 static void mainboard_enable(struct device *dev)

src/mainboard/google/skyrim/variants/baseboard/devicetree.cb

@@ -1,5 +1,10 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 chip soc/amd/sabrina
 	device domain 0 on
+		device ref lpc_bridge on
+			chip ec/google/chromeec
+				device pnp 0c09.0 alias chrome_ec on end
+			end
+		end
 	end # domain
 end	# chip soc/amd/sabrina

src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h

@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __MAINBOARD_EC_H__
+#define __MAINBOARD_EC_H__
+
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+#include <baseboard/gpio.h>
+#include <soc/gpio.h>
+
+#define MAINBOARD_EC_SCI_EVENTS                                                                \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)                                          \
+	 | EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)                                          \
+	 | EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)                                      \
+	 | EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)                                   \
+	 | EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW)                                       \
+	 | EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL)                                  \
+	 | EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY)                                           \
+	 | EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS)                                    \
+	 | EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD)                                 \
+	 | EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START)                                    \
+	 | EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP)                                     \
+	 | EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)                                            \
+	 | EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)                                       \
+	 | EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX))
+
+#define MAINBOARD_EC_SMI_EVENTS (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS							\
+				(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)		\
+				| EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/* EC can wake from S3 with lid, power button or mode change event */
+#define MAINBOARD_EC_S3_WAKE_EVENTS							\
+				(MAINBOARD_EC_S5_WAKE_EVENTS				\
+				| EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)	\
+				| EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)	\
+				| EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)		\
+				| EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+
+#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS)
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS								\
+				(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN)	\
+				| EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)	\
+				| EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+
+/*
+ * ACPI related definitions for ASL code.
+ */
+
+/* Set GPI for SCI */
+#define EC_SCI_GPI GEVENT_3 /* eSPI system event -> GPE 3 */
+
+/* Enable LID switch and provide wake pin for EC */
+#define EC_ENABLE_LID_SWITCH
+#define EC_ENABLE_WAKE_PIN GEVENT_5 /* AGPIO 11 -> GPE 5 */
+
+/* Enable Tablet switch */
+#define EC_ENABLE_TBMC_DEVICE
+
+#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE   /* EC Host Interface Resources */
+#define SIO_EC_ENABLE_PS2K   /* Enable PS/2 Keyboard */
+
+/* Enable EC sync interrupt */
+#define EC_ENABLE_SYNC_IRQ_GPIO
+
+/* EC sync irq */
+#define EC_SYNC_IRQ GPIO_84
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+/* Enable EC backed Keyboard Backlight in ACPI */
+#define EC_ENABLE_KEYBOARD_BACKLIGHT
+
+#endif /* __MAINBOARD_EC_H__ */