soc/amd/sabrina: drop CPPC code
The CPPC feature isn't available on the Sabrina SoC, so drop the corresponding code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I71a1b0717571729ebca3600ac433e621cafc4e61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Felix Held
parent
1c3b2a706e
commit
cbf290c692
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@ -33,7 +33,6 @@ romstage-y += uart.c
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ramstage-y += acpi.c
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ramstage-y += agesa_acpi.c
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ramstage-y += chip.c
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ramstage-y += cppc.c
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ramstage-y += cpu.c
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ramstage-y += data_fabric.c
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ramstage-y += fch.c
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@ -21,7 +21,6 @@
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#include <soc/msr.h>
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#include <types.h>
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#include "chip.h"
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#include <soc/cppc.h>
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unsigned long acpi_fill_madt(unsigned long current)
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{
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@ -359,8 +358,6 @@ void generate_cpu_entries(const struct device *device)
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acpigen_write_CSD_package(cpu / threads_per_core, threads_per_core,
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CSD_HW_ALL, 0);
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generate_cppc_entries(cpu);
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acpigen_pop_len();
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}
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@ -68,13 +68,6 @@ struct soc_amd_sabrina_config {
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uint8_t system_configuration;
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uint8_t cppc_ctrl;
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uint8_t cppc_perf_limit_max_range;
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uint8_t cppc_perf_limit_min_range;
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uint8_t cppc_epp_max_range;
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uint8_t cppc_epp_min_range;
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uint8_t cppc_preferred_cores;
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/* telemetry settings */
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uint32_t telemetry_vddcrvddfull_scale_current_mA;
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uint32_t telemetry_vddcrvddoffset;
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@ -1,63 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* TODO: Check if this is still correct */
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#include <acpi/acpi_pm.h>
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#include <acpi/acpigen.h>
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#include <arch/cpu.h>
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#include <soc/cppc.h>
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#include <soc/msr.h>
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/*
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* version 2 is expected to be the typical use case.
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* For now this function 'punts' on version 3 and just
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* populates the additional fields with 'unsupported'.
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*/
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void cpu_init_cppc_config(struct cppc_config *config, u32 version)
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{
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config->version = version;
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config->entries[CPPC_HIGHEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF, 8);
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config->entries[CPPC_NOMINAL_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF, 8);
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config->entries[CPPC_LOWEST_NONL_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF, 8);
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config->entries[CPPC_LOWEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF, 8);
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config->entries[CPPC_GUARANTEED_PERF] = CPPC_UNSUPPORTED;
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config->entries[CPPC_DESIRED_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_DES_PERF, 8);
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config->entries[CPPC_MIN_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MIN_PERF, 8);
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config->entries[CPPC_MAX_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MAX_PERF, 8);
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config->entries[CPPC_PERF_REDUCE_TOLERANCE] = CPPC_UNSUPPORTED;
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config->entries[CPPC_TIME_WINDOW] = CPPC_UNSUPPORTED;
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config->entries[CPPC_COUNTER_WRAP] = CPPC_UNSUPPORTED;
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config->entries[CPPC_REF_PERF_COUNTER] = CPPC_REG_MSR(MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64);
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config->entries[CPPC_DELIVERED_PERF_COUNTER] = CPPC_REG_MSR(MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64);
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config->entries[CPPC_PERF_LIMITED] = CPPC_REG_MSR(MSR_CPPC_STATUS, 1, 1);
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config->entries[CPPC_ENABLE] = CPPC_REG_MSR(MSR_CPPC_ENABLE, 0, 1);
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if (version < 2)
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return;
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config->entries[CPPC_AUTO_SELECT] = CPPC_UNSUPPORTED;
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config->entries[CPPC_AUTO_ACTIVITY_WINDOW] = CPPC_UNSUPPORTED;
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config->entries[CPPC_PERF_PREF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF, 8);
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config->entries[CPPC_REF_PERF] = CPPC_UNSUPPORTED;
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if (version < 3)
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return;
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config->entries[CPPC_LOWEST_FREQ] = CPPC_UNSUPPORTED;
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config->entries[CPPC_NOMINAL_FREQ] = CPPC_UNSUPPORTED;
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}
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void generate_cppc_entries(unsigned int core_id)
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{
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/* Generate GCPC package in first logical core */
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if (core_id == 0) {
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struct cppc_config cppc_config;
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cpu_init_cppc_config(&cppc_config, CPPC_VERSION_3);
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acpigen_write_CPPC_package(&cppc_config);
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}
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/* Write _CPC entry for each logical core */
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acpigen_write_CPPC_method();
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}
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@ -121,14 +121,6 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
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/* 0 is default */
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mcfg->system_configuration = config->system_configuration;
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/* when cppc_ctrl is 0 the other values won't be used */
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mcfg->cppc_ctrl = config->cppc_ctrl;
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mcfg->cppc_perf_limit_max_range = config->cppc_perf_limit_max_range;
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mcfg->cppc_perf_limit_min_range = config->cppc_perf_limit_min_range;
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mcfg->cppc_epp_max_range = config->cppc_epp_max_range;
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mcfg->cppc_epp_min_range = config->cppc_epp_min_range;
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mcfg->cppc_preferred_cores = config->cppc_preferred_cores;
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/* S0i3 enable */
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mcfg->s0i3_enable = config->s0ix_enable;
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mcfg->iommu_support = is_devfn_enabled(IOMMU_DEVFN);
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@ -1,15 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* TODO: Check if this is still correct */
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#ifndef AMD_SABRINA_CPPC_H
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#define AMD_SABRINA_CPPC_H
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#include <types.h>
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#include <acpi/acpigen.h>
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struct cppc_config;
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void cpu_init_cppc_config(struct cppc_config *config, u32 version);
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void generate_cppc_entries(unsigned int core_id);
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#endif /* AMD_SABRINA_CPPC_H */
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@ -1,7 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* TODO: Check if this is still correct */
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#ifndef AMD_SABRINA_MSR_H
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#define AMD_SABRINA_MSR_H
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@ -23,21 +21,6 @@
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#define PSTATE_DEF_LO_FREQ_MUL_MASK (0xFF << PSTATE_DEF_LO_FREQ_MUL_SHIFT)
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#define PSTATE_DEF_LO_CORE_FREQ_BASE 25
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#define MSR_CPPC_CAPABILITY_1 0xc00102b0
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#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24
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#define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16
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#define SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF 8
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#define SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF 0
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#define MSR_CPPC_ENABLE 0xc00102b1
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#define MSR_CPPC_REQUEST 0xc00102b3
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#define SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF 24
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#define SHIFT_CPPC_REQUEST_DES_PERF 16
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#define SHIFT_CPPC_REQUEST_MIN_PERF 8
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#define SHIFT_CPPC_REQUEST_MAX_PERF 0
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#define MSR_CPPC_STATUS 0xc00102b4
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#define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe7
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#define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe8
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