intel/fsp_baytrail: Fix LPE initialization and enable ACPI mode
This change properly assigns resources to the LPE (Low Power Engine for Audio) and enables ACPI mode. lpe.c was copied from intel/baytrail with a few minor adjustment for the different config structure. ACPI mode requires setting LpeAcpiModeEnable=LPE_ACPI_MODE_ENABLED and applying the patch that disables clearing gnvs. https://review.coreboot.org/#/c/14040/ Change-Id: I3fff9aa158bde88e571082642d4f985a5ae1976e Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/14041 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Ben Gardner
Martin Roth
parent
983608daa5
commit
cbfec89037
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@ -49,6 +49,7 @@ romstage-y += reset.c
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ramstage-y += reset.c
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ramstage-y += cpu.c
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ramstage-y += acpi.c
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ramstage-y += lpe.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c
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@ -342,6 +342,10 @@ struct soc_intel_fsp_baytrail_config {
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uint8_t DIMMtFAW;
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#define DIMM_TFAW_DEFAULT UPD_DEFAULT
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/* LPE Audio Clock configuration. */
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int lpe_codec_clk_freq; /* 19 or 25 are valid. */
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int lpe_codec_clk_num; /* Platform clock pins. [0:5] are valid. */
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/* ***** ACPI configuration ***** */
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/* Options for these are in src/arch/x86/include/arch/acpi.h */
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uint8_t fadt_pm_profile;
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@ -0,0 +1,185 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <reg_script.h>
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#include <soc/iomap.h>
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#include <soc/iosf.h>
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#include <soc/lpc.h>
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#include <soc/nvs.h>
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#include <soc/pattrs.h>
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#include <soc/pci_devs.h>
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#include <soc/pmc.h>
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#include <soc/ramstage.h>
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#include "chip.h"
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/* The LPE audio devices needs 1MiB of memory reserved aligned to a 512MiB
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* address. Just take 1MiB @ 512MiB. */
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#define FIRMWARE_PHYS_BASE (512 << 20)
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#define FIRMWARE_PHYS_LENGTH (1 << 20)
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#define FIRMWARE_PCI_REG_BASE 0xa8
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#define FIRMWARE_PCI_REG_LENGTH 0xac
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#define FIRMWARE_REG_BASE_C0 0x144000
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#define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4)
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static void assign_device_nvs(device_t dev, u32 *field, unsigned index)
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{
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struct resource *res;
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res = find_resource(dev, index);
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if (res)
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*field = res->base;
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}
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static void lpe_enable_acpi_mode(device_t dev)
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{
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static const struct reg_script ops[] = {
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/* Disable PCI interrupt, enable Memory and Bus Master */
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REG_PCI_OR32(PCI_COMMAND,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)),
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/* Enable ACPI mode */
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REG_IOSF_OR(IOSF_PORT_0x58, LPE_PCICFGCTR1,
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LPE_PCICFGCTR1_PCI_CFG_DIS |
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LPE_PCICFGCTR1_ACPI_INT_EN),
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REG_SCRIPT_END
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};
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global_nvs_t *gnvs;
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/* Find ACPI NVS to update BARs */
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gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS);
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if (!gnvs) {
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printk(BIOS_ERR, "Unable to locate Global NVS\n");
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return;
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}
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/* Save BAR0, BAR1, and firmware base to ACPI NVS */
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assign_device_nvs(dev, &gnvs->dev.lpe_bar0, PCI_BASE_ADDRESS_0);
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assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_1);
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assign_device_nvs(dev, &gnvs->dev.lpe_fw, FIRMWARE_PCI_REG_BASE);
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/* Device is enabled in ACPI mode */
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gnvs->dev.lpe_en = 1;
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/* Put device in ACPI mode */
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reg_script_run_on_dev(dev, ops);
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}
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static void setup_codec_clock(device_t dev)
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{
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uint32_t reg;
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u32 *clk_reg;
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struct soc_intel_fsp_baytrail_config *config;
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const char *freq_str;
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config = dev->chip_info;
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switch (config->lpe_codec_clk_freq) {
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case 19:
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freq_str = "19.2";
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reg = CLK_FREQ_19P2MHZ;
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break;
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case 25:
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freq_str = "25";
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reg = CLK_FREQ_25MHZ;
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break;
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default:
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printk(BIOS_DEBUG, "LPE codec clock not required.\n");
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return;
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}
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/* Default to always running. */
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reg |= CLK_CTL_ON;
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if (config->lpe_codec_clk_num < 0 || config->lpe_codec_clk_num > 5) {
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printk(BIOS_DEBUG, "Invalid LPE codec clock number.\n");
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return;
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}
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printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str);
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clk_reg = (u32 *)(PMC_BASE_ADDRESS + PLT_CLK_CTL_0);
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clk_reg += config->lpe_codec_clk_num;
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write32(clk_reg, (read32(clk_reg) & ~0x7) | reg);
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}
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static void lpe_stash_firmware_info(device_t dev)
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{
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struct resource *res;
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struct resource *mmio;
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const struct pattrs *pattrs = pattrs_get();
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res = find_resource(dev, FIRMWARE_PCI_REG_BASE);
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if (res == NULL) {
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printk(BIOS_DEBUG, "LPE Firmware memory not found.\n");
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return;
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}
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/* Continue using old way of informing firmware address / size. */
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pci_write_config32(dev, FIRMWARE_PCI_REG_BASE, res->base);
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pci_write_config32(dev, FIRMWARE_PCI_REG_LENGTH, res->size);
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/* C0 and later steppings use an offset in the MMIO space. */
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if (pattrs->stepping >= STEP_C0) {
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mmio = find_resource(dev, PCI_BASE_ADDRESS_0);
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write32((u32 *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0),
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res->base);
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write32((u32 *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0),
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res->size);
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}
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}
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static void lpe_init(device_t dev)
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{
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struct soc_intel_fsp_baytrail_config *config = dev->chip_info;
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lpe_stash_firmware_info(dev);
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setup_codec_clock(dev);
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if (config->LpeAcpiModeEnable == LPE_ACPI_MODE_ENABLED)
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lpe_enable_acpi_mode(dev);
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}
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static void lpe_read_resources(device_t dev)
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{
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pci_dev_read_resources(dev);
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reserved_ram_resource(dev, FIRMWARE_PCI_REG_BASE,
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FIRMWARE_PHYS_BASE >> 10,
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FIRMWARE_PHYS_LENGTH >> 10);
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}
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static const struct device_operations device_ops = {
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.read_resources = lpe_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = lpe_init,
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.enable = NULL,
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.scan_bus = NULL,
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.ops_pci = &soc_pci_ops,
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};
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static const struct pci_driver southcluster __pci_driver = {
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.ops = &device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = LPE_DEVID,
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};
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