soc/intel/common/cse_lite: Defer cse_fw_sync for JSL

Defer cse_fw_sync to BS_DEV_RESOURCES boot state so that MRC training
data can be cached before CSE FW Sync and a second MRC training can be
avoided.

BUG=b:168850641
TEST=Build and boot the waddledoo board to OS. Ensure that the memory
training is performed only once.

Change-Id: I0ef5693eaa6ed34dc08c94e5db153f4295578f5f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>

src/soc/intel/common/block/cse/cse_lite.c

@@ -751,7 +751,7 @@ void cse_fw_sync(void *unused)
 	}
 }
 
-#if CONFIG(SOC_INTEL_TIGERLAKE)
+#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_JASPERLAKE)
 /*
  * This needs to happen after the MRC cache write to avoid a 2nd
  * memory training sequence.