From cc0b4527a69530c9a9a97aec265a84b85ca90ea2 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 6 May 2022 17:04:41 +0200 Subject: [PATCH] nb/intel/gm45/iommu.c: Fix clearing GTT This was dead code as it was checking for the wrong bit (bit 11 indicates the use of shadow GTT). It was doing it at the wrong place regardless as no BARs are set up. Move the code clearing GTT into the GMA .init code and do it unconditionally: if the GTT does not match 2M then the cycles are simply not decoded. Tested on thinkpad X200. Change-Id: Iac3264d484e66e9ca4b3cd3df90ad87a476e31ce Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/64123 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/northbridge/intel/gm45/gma.c | 11 +++++++++-- src/northbridge/intel/gm45/iommu.c | 17 ----------------- 2 files changed, 9 insertions(+), 19 deletions(-) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index d5e9c48dc6..79b366f885 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -156,8 +156,15 @@ static void gma_func0_init(struct device *dev) return; mmio = res2mmio(gtt_res, 0, 0); - if (!CONFIG(NO_GFX_INIT)) - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + /* + * GTT base is at a 2M offset and is 2M big. If GTT is smaller than 2M + * cycles are simply not decoded which is fine. + */ + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + memset(mmio + 2 * MiB, 0, 2 * MiB); + + if (CONFIG(NO_GFX_INIT)) + pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MASTER); if (!CONFIG(MAINBOARD_USE_LIBGFXINIT)) { /* PCI Init, will run VBIOS */ diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 4199f8bb1d..4f6e000bdc 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -30,23 +30,6 @@ void init_iommu(void) } mchbar_write32(0x20, IOMMU_BASE4 | 1); /* all other DMA sources */ - /* clear GTT */ - u16 gtt = pci_read_config16(PCI_DEV(0, 0, 0), D0F0_GGC); - if (gtt & 0x400) { /* VT mode */ - const pci_devfn_t igd = PCI_DEV(0, 2, 0); - - /* setup somewhere */ - pci_or_config16(igd, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - void *bar = (void *)pci_read_config32(igd, PCI_BASE_ADDRESS_0); - - /* clear GTT, 2MB is enough (and should be safe) */ - memset(bar, 0, 2<<20); - - /* and now disable again */ - pci_and_config16(igd, PCI_COMMAND, ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY)); - pci_write_config32(igd, PCI_BASE_ADDRESS_0, 0); - } - if (stepping == STEPPING_B3) { mchbar_setbits8(0xffc, 1 << 4); const pci_devfn_t peg = PCI_DEV(0, 1, 0);